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12-Bit, 4.0Gsps High-Dynamic Performance Wideband DAC

12-Bit, 4.0Gsps DAC Delivers -164dBm/Hz Noise Density at 1180mW

Product Details

Key Features

Parametric specs for High-Speed DACs (≥ 1MHz)
Resolution (bits) 12
# Channels 1
fCLK (Msps) 4000
SFDR (dBc) (@ fOUT) 70 @ 800MHz
DNL (±LSB) 0.8
INL (±LSB) 1.2
IOUT (mA) 20
PDISS (mW) 1180
Interface Interleaved, LVDS
VSUPPLY (V) 3.3
Package/Pins CSBGA/169
Budgetary
Price (See Notes)
0
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Parameters

Parametric specs for High-Speed DACs (≥ 1MHz)
Resolution (bits) 12
# Channels 1
fCLK (Msps) 4000
SFDR (dBc) (@ fOUT) 70 @ 800MHz
DNL (±LSB) 0.8
INL (±LSB) 1.2
IOUT (mA) 20
PDISS (mW) 1180
Interface Interleaved, LVDS
VSUPPLY (V) 3.3
Package/Pins CSBGA/169
Budgetary
Price (See Notes)
0

Key Features

  • 4.0Gsps Output Update Rate
  • Industry-Leading Dynamic Performance
    • SFDR* = 76dBc at fOUT = 400MHz
    • SFDR* = 70dBc at fOUT = 800MHz
    • Wideband Noise Spectral Density = -164dBm/Hz
  • Low-Power Operation
    • 770mW (fDAC = 2000Msps)
    • 1180mW (fDAC = 4000Msps)
  • 4:1 Multiplexed LVDS Inputs
    • Up to 1000Mwps each port
  • Internal 50Ω Differential Output Termination
  • Input Register Scan Mode for In-Circuit Continuity Verification
  • Compact 11mm x 11mm, 169 CSBGA Package
  • Evaluation Kit Available (Order MAX19693EVKIT)

Applications/Uses

  • Digital IF Generation in X-Band Transmitters
  • Direct Digital Synthesis
  • Electronic Warfare
  • Radar Waveform and LO Signal Synthesis

Description

The MAX19693 12-bit, 4.0Gsps digital-to-analog converter (DAC) enables direct digital synthesis of high-frequency and wideband signals. The DAC has been optimized for wideband communications and radar applications. The MAX19693 provides excellent spurious and noise performance and can be used for synthesis of wideband signals in the frequency range from DC to nearly 2GHz. The 4.0Gsps update rate enables digital synthesis of signals with more than 1.5GHz bandwidth.

The MAX19693 includes four 12-bit multiplexed low-voltage differential signaling (LVDS) input ports, each operating at up to 1GHz in double data rate (DDR) or quad data rate (QDR) mode. The DAC accepts a clock at 1/2 the DAC update rate, as conversion is triggered on both rising and falling clock edges. The input data rate is 1/4 the DAC update rate (1/2 the clock rate). The MAX19693 provides an LVDS data clock output to simplify interfacing to FPGA or ASIC devices.

The MAX19693 is a current-steering DAC with an integrated, self-calibrated 50Ω differential output termination to ensure optimum dynamic performance. The MAX19693 operates from 3.3V and 1.8V power supplies and consumes 1180mW at 4.0Gsps. The MAX19693 is specified over the extended temperature range (-40°C to +85°C) and is available in a compact 11mm x 11mm, 169 CSBGA package.

Simplified Block Diagram

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .