Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
DescriptionThe MAX1196 is a 3V, dual 8-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving two ADCs. The MAX1196 is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumentation, and digital communications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 87mW while delivering a typical signal-to-noise and distortion (SINAD) of 48.4dB at an input frequency of 20MHz and a sampling rate of 40Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters can also be operated with single-ended inputs. In addition to low operating power, the MAX1196 features a 3mA sleep mode as well as a 0.1µA power-down mode to conserve power during idle periods.
An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired for applications requiring increased accuracy or a different input voltage range.
The MAX1196 features parallel, multiplexed, CMOS-compatible three-state outputs. The digital output format can be set to two's complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing. The MAX1196 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range.
See a parametric table of the complete family of pin-compatible, 8-bit high-speed ADCs.
For a 10-bit, pin-compatible upgrade, refer to the MAX1186 data sheet. With the N.C. pins of the MAX1196 internally pulled down to ground, this ADC becomes a drop-in replacement for the MAX1186.
- Single 2.7V to 3.6V Operation
- Excellent Dynamic Performance
- 48.4dB/44.7dB SINAD at fIN = 20MHz/200MHz
- 68.9dB/53dBc SFDR at fIN = 20MHz/200MHz
- -72dB Interchannel Crosstalk at fIN = 20MHz
- Low Power
- 87mW (Normal Operation)
- 9mW (Sleep Mode)
- 0.3µW (Shutdown Mode)
- 0.05dB Gain and ±0.05° Phase Matching
- Wide ±1VP-P Differential Analog Input Voltage Range
- 400MHz -3dB Input Bandwidth
- On-Chip 2.048V Precision Bandgap Reference
- User-Selectable Output Format—Two's Complement or Offset Binary
- Pin-Compatible 8-Bit and 10-Bit Upgrades Available
- Baseband I/Q Sampling
- Battery-Powered Instrumentation
- Multichannel IF Sampling
- Set-Top Boxes
- Ultrasound and Medical Imaging
- VSAT Terminals
- WLAN, WWAN, WLL, MMDS Modems
|Part Number||Input Chan.||Resolution|
|Full Pwr. BW|
|Data Bus Interface||Package/Pins||Budgetary|
|max ≥||min||min||See Notes|
Technical DocumentsTutorial 4294 Differential Gain and Phase—Why Measure It, if You Cannot See It?
App Note 2771 High-Speed ADC Sets Input Common-Mode Range
Tutorial 1819 Selecting the Optimum Test Tones and Test Equipment for Successful High-Speed ADC Sinewave Testing
Tutorial 1040 Coherent Sampling vs. Window Sampling
Tutorial 729 Dynamic Testing of High-Speed ADCs, Part 2
Tutorial 728 Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1
Additional ResourcesEvaluation Kit: MAX1198EVKIT
|Device||Fab Process||Technology||Sample size||Rejects||FIT at 25°C||FIT at 55°C||Material Composition|
|Tutorial||4294||Differential Gain and Phase—Why Measure It, if You Cannot See It?|
|App Note||2771||High-Speed ADC Sets Input Common-Mode Range|
|Tutorial||1819||Selecting the Optimum Test Tones and Test Equipment for Successful High-Speed ADC Sinewave Testing|
|Tutorial||1040||Coherent Sampling vs. Window Sampling|
|Tutorial||729||Dynamic Testing of High-Speed ADCs, Part 2|
|Tutorial||728||Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1|