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12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications

Product Details

Key Features

Applications/Uses

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Key Features

  • 170Msps Conversion Rate
  • SNR = 64.3dB, fIN = 100MHz at 170Msps
  • SFDR = 73dBc, fIN = 100MHz at 170Msps
  • ±0.7 LSB INL, ±0.25 DNL (typ)
  • 907mW Power Dissipation at 170Msps
  • On-Chip Selectable Divide-by-2 Clock Input
  • Parallel or Demux Parallel Digital CMOS Outputs
  • Reset Option for Synchronizing Multiple ADCs
  • Data Clock Output
  • Offset Binary or Two's-Complement Output
  • Evaluation Kit Available (MAX19542EVKIT)

Applications/Uses

  • Base-Station Power-Amplifier Linearization
  • Cable Head-End Receivers
  • Communications Test Equipment
  • Radar and Satellite Subsystems
  • Wireless and Wired Broadband Communication

Description

The MAX19542 monolithic 12-bit, 170Msps analog-to-digital converter (ADC) is optimized for outstanding dynamic performance at high-IF frequencies of 300MHz and beyond. This device operates with conversion rates up to 170Msps while consuming only 907mW.

At 170Msps and an input frequency of 240MHz, the MAX19542 achieves a spurious-free dynamic range (SFDR) of 76.4dBc. The MAX19542 features an excellent signal-to-noise ratio (SNR) of 65dB at 10MHz that remains flat (within 3dB) for input tones up to 250MHz. This makes the MAX19542 ideal for wideband applications such as power-amplifier predistortion in cellular base-station transceiver systems.

The MAX19542 operates in either parallel mode where the data outputs appear on a single parallel port at the sampling rate, or in demux parallel mode, where the outputs appear on two separate parallel ports at one-half the sampling rate. See the Modes of Operation section in the full data sheet.

The MAX19542 operates on a single 1.8V supply. The analog input is differential and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit that allows clock frequencies as high as 340MHz. This helps to reduce the phase noise of the input clock source, allowing for higher dynamic performance. For best performance, a differential LVPECL sampling clock is recommended. The digital outputs are CMOS compatible and the data format can be selected to be either two's complement or offset binary.

A pin-compatible, 12-bit, 125Msps version of the MAX19542 is also available. Refer to the MAX19541 data sheet for more information.

The MAX19542 is available in a 68-pin QFN with exposed pad (EP) and is specified over the extended (-40°C to +85°C) temperature range.

See a parametric table of the complete family of pin-compatible, 12-bit high-speed ADCs.

Simplified Block Diagram

MAX19542: Functional Diagram MAX19542: Functional Diagram Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .