Simplified Block Diagram
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- 69dB SNR for Excellent Receiver Sensitivity and Image Resolution
- 8 Channels in a Small (10mm x 10mm) Package for Multichannel Receiver Architectures
- Ultra-Low Power for Reduced Heat Dissipation and Improved Reliability
- Serial LVDS Outputs for Reduced FPGA Interface Pin Count, Reduced PCB Layout Complexity, and Reduced Digital-Interface Radiated RF Emissions
- Programmable Serial Test Patterns for Improved Ease of Design and Test