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Dual-Channel, 8-Bit, 100Msps ADC

8-Bit, 100Msps Dual-Channel ADC Provides 49.8dBFS SNR and 69dBc SFDR at 57mW per Channel

Product Details

Key Features

Applications/Uses

Parametric specs for High-Speed ADCs (> 5Msps)
Resolution (bits) 8
# Input Channels 2
Sample Rate (Msps) (max) 100
Data Bus Interface Selectable Dual/Mux'd CMOS
AC Specs (MHz) (@ fIN) 70
SFDR (dBc) (min) 77
SINAD (dB) 49.3
SNR (dB) 49.8
THD (dB) -72
DNL (±LSB) 0.1
INL (±LSB) 0.1
Package/Pins TQFN/48
Budgetary
Price (See Notes)
7.23
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Simplified Block Diagram

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Parameters

Parametric specs for High-Speed ADCs (> 5Msps)
Resolution (bits) 8
# Input Channels 2
Sample Rate (Msps) (max) 100
Data Bus Interface Selectable Dual/Mux'd CMOS
AC Specs (MHz) (@ fIN) 70
SFDR (dBc) (min) 77
SINAD (dB) 49.3
SNR (dB) 49.8
THD (dB) -72
DNL (±LSB) 0.1
INL (±LSB) 0.1
Package/Pins TQFN/48
Budgetary
Price (See Notes)
7.23

Key Features

  • Very-Low-Power Operation (57mW/Channel at 100Msps)
  • 1.8V or 2.5V to 3.3V Analog Supply
  • Excellent Dynamic Performance
    • 49.8dBFS SNR at 70MHz
    • 69dBc SFDR at 70MHz
  • User-Programmable Adjustments and Feature Selection through an SPI™ Interface
  • Selectable Data Bus (Dual CMOS or Single Multiplexed CMOS)
  • DCLK Output and Programmable Data Output Timing Simplifies High-Speed Digital Interface
  • Very Wide Input Common-Mode Voltage Range (0.4V to 1.4V)
  • Very High Analog Input Bandwidth (> 850MHz)
  • Single-Ended or Differential Analog Inputs
  • Single-Ended or Differential Clock Input
  • Divide-by-One (DIV1), Divide-by-Two (DIV2), and Divide-by-Four (DIV4) Clock Modes
  • Two's Complement, Gray Code, and Offset Binary Output Data Format
  • Out-of-Range Indicator (DOR)
  • CMOS Output Internal Termination Options (Programmable)
  • Reversible Bit Order (Programmable)
  • Data Output Test Patterns
  • Small 7mm x 7mm, 48-Pin Thin QFN Package with Exposed Pad

Applications/Uses

  • Digital Set-Top Boxes
  • IF and Baseband Communications, Including Cellular Base Stations and Point-to-Point Microwave Receivers
  • Portable Instrumentation and Low-Power Data Acquisition
  • Ultrasound and Medical Imaging

Description

The MAX19506 dual-channel, analog-to-digital converter (ADC) provides 8-bit resolution and a maximum sample rate of 100Msps.

The MAX19506 analog input accepts a wide 0.4V to 1.4V input common-mode voltage range, allowing DC-coupled inputs for a wide range of RF, IF, and baseband front-end components. The MAX19506 provides excellent dynamic performance from baseband to high input frequencies beyond 400MHz, making the device ideal for zero-intermediate frequency (ZIF) and high-intermediate frequency (IF) sampling applications. The typical signal-to-noise ratio (SNR) performance is 49.8dBFS and typical spurious-free dynamic range (SFDR) is 69dBc at fIN = 70MHz and fCLK = 100MHz.

The MAX19506 operates from a 1.8V supply. Additionally, an integrated, self-sensing voltage regulator allows operation from a 2.5V to 3.3V supply (AVDD). The digital output drivers operate on an independent supply voltage (OVDD) over the 1.8V to 3.5V range. The analog power consumption is only 57mW per channel at VAVDD = 1.8V. In addition to low operating power, the MAX19506 consumes only 1mW in power-down mode and 17mW in standby mode.

Various adjustments and feature selections are available through programmable registers that are accessed through the 3-wire serial-port interface. Alternatively, the serial-port interface can be disabled, with the three pins available to select output mode, data format, and clock-divider mode. Data outputs are available through a dual parallel CMOS-compatible output data bus that can also be configured as a single multiplexed parallel CMOS bus.

The MAX19506 is available in a small 7mm x 7mm, 48-pin thin QFN package and is specified over the -40°C to +85°C extended temperature range.

Refer to the MAX19515, MAX19516, and MAX19517 data sheets for pin- and feature-compatible 10-bit, 65Msps, 100Msps, and 130Msps versions, respectively. Refer to the MAX19505 and MAX19507 data sheets for pin- and feature-compatible 8-bit, 65Msps and 130Msps versions, respectively.

Simplified Block Diagram

MAX19506: Functional Diagram MAX19506: Functional Diagram Zoom icon

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .