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MAX1449

10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference

3.3V, 10-Bit, 105Msps ADC Delivers 70dBc SFDR

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Overview

Description

The MAX1449 3.3V, 10-bit analog-to-digital converter (ADC) features a fully differential input, a pipelined 10-stage ADC architecture with wideband track-and-hold (T/H), and digital error correction incorporating a fully differential signal path. The ADC is optimized for lowpower, high-dynamic performance in imaging and digital communications applications. The converter operates from a single 2.7V to 3.6V supply, consuming only 186mW while delivering a 58.5dB (typ) signal-to-noise ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a -3dB 400MHz bandwidth and may be operated with single-ended inputs. In addition to low operating power, the MAX1449 features a 5µA power-down mode for idle periods.

An internal 2.048V precision bandgap reference is used to set the ADC's full-scale range. A flexible reference structure allows the user to supply a buffered, direct, or externally derived reference for applications requiring increased accuracy or a different input voltage range.

See a parametric table of the complete family of pin-compatible, 10-bit high-speed ADCs.

The MAX1449 has parallel, offset binary, CMOS-compatible, three-state outputs that can be operated from 1.7V to 3.6V to allow flexible interfacing. The device is available in a 5mm x 5mm 32-pin TQFP package and is specified over the extended industrial (-40°C to +85°C) temperature range.

MAX1449: Functional Diagram

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Key Features

Single 3.3V Operation
Excellent Dynamic Performance
- 58.5dB SNR at f_IN = 20MHz
- 72dBc SFDR at f_IN = 20MHz
Low Power
- 62mA (Normal Operation)
- 5µA (Shutdown Mode)
Fully Differential Analog Input
Wide 2V_P-P Differential Input Voltage Range
400MHz -3dB Input Bandwidth
On-Chip 2.048V Precision Bandgap Reference
CMOS-Compatible Three-State Outputs
32-Pin TQFP Package
Evaluation Kit Available (MAX1448 EV Kit)

Applications/Uses

Baseband and IF Digitization
CCD Imaging
Digital Set-Top Boxes
Ultrasound Imaging
Video Digitizing Applications

Parametric Specs

Part Number

Input Chan.

Resolution
(bits)

Sample Rate
(Msps)

AC Specs
(MHz)

SFDR
(dBc)

ENOB
(bits)

SINAD
(dB)

SNR
(dB)

THD
(dB)

DNL
(±LSB)

INL
(±LSB)

Full Pwr. BW
(MHz)

I_CC
(mA)

Data Bus Interface

Package/Pins

Budgetary
Price

max ≥

@ f_IN

min

typ

See Notes

MAX1449

105

9.3

58.5

-70

0.5

0.75

400

µP/10

TQFP/32

$24.02 @1k

See All High-Speed ADCs (> 5Msps) (53)

Pricing Notes:

This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific and version-specific prices and delivery, please see the price and availability page or contact an authorized distributor.

Design Resources

Technical Documents

Tutorial 4294 Differential Gain and Phase—Why Measure It, if You Cannot See It?
App Note 3292 Crunching FFTs with Microsoft Excel
App Note 3228 Improving Gain Flatness without Sacrificing Dynamic Performance in High-IF ADCs
App Note 3190 Coherent Sampling Calculator (CSC)
App Note 2882 Proper Input Network Selection Achieves Optimum Dynamic Performance and Excellent Gain Flatness in High-Speed ADCs
Tutorial 1819 Selecting the Optimum Test Tones and Test Equipment for Successful High-Speed ADC Sinewave Testing
Tutorial 1040 Coherent Sampling vs. Window Sampling
Tutorial 989 Multiply Your Sampling Rate with Time-Interleaved Data Converters
Tutorial 810 Understanding Flash ADCs
Tutorial 729 Dynamic Testing of High-Speed ADCs, Part 2
Tutorial 728 Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1

Quality and Environmental Data

Product Reliability Reports: MAX1449.pdf
Lead-Free Package Tin (Sn) Whisker Reports

Quality And Environmental

Device	Fab Process	Technology	Sample size	Rejects	FIT at 25°C	FIT at 55°C

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

Quality Management System >
Environmental Management System >

Order

Status:

Package:

Temperature:

Type	ID	Title
Tutorial	4294	Differential Gain and Phase—Why Measure It, if You Cannot See It?
App Note	3292	Crunching FFTs with Microsoft Excel
App Note	3228	Improving Gain Flatness without Sacrificing Dynamic Performance in High-IF ADCs
App Note	3190	Coherent Sampling Calculator (CSC)
App Note	2882	Proper Input Network Selection Achieves Optimum Dynamic Performance and Excellent Gain Flatness in High-Speed ADCs
Tutorial	1819	Selecting the Optimum Test Tones and Test Equipment for Successful High-Speed ADC Sinewave Testing
Tutorial	1040	Coherent Sampling vs. Window Sampling
Tutorial	989	Multiply Your Sampling Rate with Time-Interleaved Data Converters
Tutorial	810	Understanding Flash ADCs
Tutorial	729	Dynamic Testing of High-Speed ADCs, Part 2
Tutorial	728	Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1

Type

PDF

Title

Tutorial

4294

Differential Gain and Phase—Why Measure It, if You Cannot See It?

App Note

3292

Crunching FFTs with Microsoft Excel

App Note

3228

Improving Gain Flatness without Sacrificing Dynamic Performance in High-IF ADCs