Simplified Block Diagram
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- Excellent Dynamic Performance
- 69.9dB SNR at 5.3MHz
- 94dBc SFDR at 5.3MHz
- Ultra-Low Power
- 114mW per Channel (Normal Operation)
- Serial LVDS Outputs
- Pin-Selectable LVDS/SLVS (Scalable Low-Voltage Signal) Mode
- LVDS Outputs Support Up to 30in FR4 Backplane Connections
- Test Mode for Digital Signal Integrity
- Fully Differential Analog Inputs
- Wide Differential Input Voltage Range (1.4VP-P)
- On-Chip 1.24V Precision Bandgap Reference
- Clock Duty-Cycle Equalizer
- Compact, 68-Pin Thin QFN Package with Exposed Pad
- Evaluation Kit Available (Order MAX1437BEVKIT)
- Multichannel Communications
- Ultrasound and Medical Imaging
An internal 1.24V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. The reference architecture is optimized for low noise.
A single-ended clock controls the data-conversion process. An internal duty-cycle equalizer compensates for wide variations in clock duty cycle. An on-chip phase-locked loop (PLL) generates the high-speed serial low-voltage differential signal (LVDS) clock.
The MAX1438B has self-aligned serial LVDS outputs for data, clock, and frame-alignment signals. The output data is presented in two's-complement format.
The MAX1438B offers a maximum sample rate of 64Msps. This device is available in a small, 10mm x 10mm x 0.8mm, 68-pin thin QFN package with exposed pad and is specified for the extended industrial (-40°C to +85°C) temperature range.