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Key Features
Applications/Uses
| Resolution (bits) | 10 |
| # Input Channels | 8 |
| Sample Rate (Msps) (max) | 50 |
| Data Bus Interface | Serial LVDS |
| AC Specs (MHz) (@ fIN) | 19.3 |
| SFDR (dBc) (min) | 85 |
| ENOB (bits) (min) | 9.9 |
| SINAD (dB) | 61.1 |
| SNR (dB) | 61.1 |
| THD (dB) | -91 |
| DNL (±LSB) | 0.1 |
| INL (±LSB) | 0.1 |
| Package/Pins | TQFP/100 |
| Budgetary Price (See Notes) | 76.56 |
Simplified Block Diagram
Technical Docs
| Data Sheet | Octal, 10-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs | Apr 11, 2011 |
Support & Training
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Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.
Parameters
| Resolution (bits) | 10 |
| # Input Channels | 8 |
| Sample Rate (Msps) (max) | 50 |
| Data Bus Interface | Serial LVDS |
| AC Specs (MHz) (@ fIN) | 19.3 |
| SFDR (dBc) (min) | 85 |
| ENOB (bits) (min) | 9.9 |
| SINAD (dB) | 61.1 |
| SNR (dB) | 61.1 |
| THD (dB) | -91 |
| DNL (±LSB) | 0.1 |
| INL (±LSB) | 0.1 |
| Package/Pins | TQFP/100 |
| Budgetary Price (See Notes) | 76.56 |
Key Features
- Excellent Dynamic Performance
- 61dB SNR at 5.3MHz
- 84dBc SFDR at 5.3MHz
- 94dB Channel Isolation
- Ultra-Low Power
- 96mW per Channel (Normal Operation)
- Serial LVDS Outputs
- Pin-Selectable LVDS/SLVS (Scalable Low-Voltage Signal) Mode
- LVDS Outputs Support Up to 30 Inches FR-4 Backplane Connections
- Test Mode for Digital Signal Integrity
- Fully Differential Analog Inputs
- Wide Differential Input Voltage Range (1.4VP-P)
- On-Chip 1.24V Precision Bandgap Reference
- Clock Duty-Cycle Equalizer
- Compact, 100-Pin TQFP Package with Exposed Pad
- Evaluation Kit Available (Order MAX1434EVKIT)
Applications/Uses
- Instrumentation
- Multichannel Communications
- Ultrasound and Medical Imaging
Description
An internal 1.24V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range. The reference architecture is optimized for low noise.
A single-ended clock controls the data-conversion process. An internal duty-cycle equalizer compensates for wide variations in clock duty cycle. An on-chip PLL generates the high-speed serial low-voltage differential signal (LVDS) clock.
The MAX1434 has self-aligned serial LVDS outputs for data, clock, and frame-alignment signals. The output data is presented in two's complement or binary format.
The MAX1434 offers a maximum sample rate of 50Msps. See the Pin-Compatible Versions table in the full data sheet for 12-bit versions. This device is available in a small, 14mm x 14mm x 1mm, 100-pin TQFP package with exposed pad and is specified for the extended industrial (-40°C to +85°C) temperature range.
Technical Docs
| Data Sheet | Octal, 10-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs | Apr 11, 2011 |
Support & Training
Search our knowledge base for answers to your technical questions.
Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .
Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.
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