Simplified Block Diagram
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- 1.8V to 3.6V Single Digital Supply Operation
- Internal Charge Pump for Analog Circuits (2.7V to 5.5V)
- 12-Bit SAR ADC
- 12 Bits, 312ksps, No Missing Codes
- 16 Bits, 1000sps, DSP Mode
- 16-Word FIFO and 20-Bit Accumulator
- PGA with Gains of 1, 2, 4, and 8
- Unipolar and Bipolar Modes
- 16-Input Differential Multiplexer
- Dual 12-Bit Force-Sense DACs
- 16-Word FIFO (DACA Only)
- Independent Voltage References for ADC and DACs
- Internal 2.5V Reference
- Adjustable Reference Buffers Provide 1.25V, 2.048V, or 2.5V
- System Support
- ADC Alarm Register
- Uncommitted Op Amps
- Dual SPDT Analog Switches
- Internal/External Temperature Sensor
- Internal Oscillator with Clock I/O
- Digital Programmable I/O
- Analog Programmable I/O
- Programmable Interrupts
- Accurate Supply Voltage Measurement
- Programmable Dual Voltage Monitors
- SPI-/QSPI-/MICROWIRE-Compatible, 4-Wire Serial Interface
- Space-Saving, 6mm x 6mm, 40-Pin Thin QFN Package
- Battery-Powered and Portable Devices
- Data Acquisition Systems
- Electrochemical and Optical Sensors
- Low-Cost CODECs
- Medical Instruments
The MAX1329/MAX1330 offer a single ADC with a reference buffer. The ADC is capable of operating in one of two user-programmable modes. In normal mode, the ADC provides up to 12 bits of resolution at 312ksps. In DSP mode, the ADC provides up to 16 bits of resolution at 1000sps. The ADC accepts one external differential input or two external single-ended inputs as well as inputs from other circuitry on-board. An on-chip programmable gain amplifier (PGA) follows the analog inputs, reducing external circuitry requirements. The PGA gain is adjustable from 1V/V to 8V/V.
The MAX1329/MAX1330 operate from a 1.8V to 3.6V digital power supply. Shutdown and sleep modes are available for power-saving applications. Under normal operation, an internal charge pump boosts the supply voltage for the analog circuitry when the supply is < 2.7V.
The MAX1329/MAX1330 offer four analog programmable I/Os (APIOs) and four digital programmable I/Os (DPIOs). The APIOs can be configured as general-purpose logic inputs and outputs, as a wake-up function, or as a buffer and level shifter for the serial interface to communicate with slave devices powered by the analog supply, AVDD. The DPIOs can be configured as general-purpose logic inputs and outputs as well as inputs to directly control the ADC conversion rate, the analog switches, the loading of the DACs, wake-up, sleep, and shutdown modes, and as an interrupt for when the analog-to-digital conversion is complete.
The MAX1329 includes dual 12-bit force-sense DACs with a programmable reference buffer and one op amp. The MAX1330 provides one 12-bit force-sense DAC with a programmable reference buffer and two op amps. For the MAX1329/MAX1330, a 16-word DAC FIFO can be used with the DACA for direct digital synthesis (DDS) of waveforms.
The 4-wire serial interface is compatible with SPI™, QSPI™, and MICROWIRE™.