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14-Bit, 80Msps, 3.3V ADC

Product Details

Key Features

Simplified Block Diagram

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Sampling:
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Key Features

  • Direct IF Sampling Up to 400MHz
  • Excellent Dynamic Performance
    • 72.4dB/70.9dB SNR at fIN = 3MHz/175MHz
    • 86.2dBc/82.5dBc SFDR at fIN = 3MHz/175MHz
  • Low Noise Floor: -74.8dBFS
  • 3.3V Low-Power Operation
    • 396mW (Single-Ended Clock Mode)
    • 429mW (Differential Clock Mode)
    • 300µW (Power-Down Mode)
  • Fully Differential or Single-Ended Analog Input
  • Adjustable Full-Scale Analog Input Range
    • ±0.35V to ±1.10V
  • Common-Mode Reference
  • CMOS-Compatible Outputs in Two's Complement or Gray Code
  • Data-Valid Indicator Simplifies Digital Interface
  • Data Out-of-Range Indicator
  • Miniature, 6mm x 6mm x 0.8mm 40-Pin Thin QFN Package with Exposed Paddle
  • Evaluation Kit Available (Order MAX12555EVKIT)

Applications/Uses

  • IF and Baseband Communication Receivers: Cellular, Point-to-Point Microwave, HFC, WLAN
  • Low-Power Data Acquisition
  • Medical Imaging Including Positron Emission Tomography (PET)
  • Portable Instrumentation
  • Video Imaging

Description

The MAX12554 is a 3.3V, 14-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts single- ended or differential signals. The MAX12554 is optimized for high dynamic performance, low power, and small size. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12554 ideal for intermediate frequency (IF) sampling applications.

Powered from a single 3.3V supply, the MAX12554 consumes only 429mW while delivering a typical 70.9dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. In addition to low operating power, the MAX12554 features a 300µW power-down mode to conserve power during idle periods.

A flexible reference structure allows the MAX12554 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.10V. The MAX12554 provides a common- mode reference to simplify design and reduce external component count in differential analog input circuits.

The MAX12554 supports either a single-ended or differential input clock. Wide variations in the clock duty cycle are compensated with the ADC's internal dutycycle equalizer (DCE).

ADC conversion results are available through a 14-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two's complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide 1.7V to 3.6V supply, allowing the MAX12554 to interface with various logic levels.

The MAX12554 is available in a 6mm x 6mm x 0.8mm, 40-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40°C to +85°C) temperature range.

See a parametric table of the complete family of pin-compatible, 12-/14-bit high-speed ADCs.

Simplified Block Diagram

MAX12554: Functional Diagram MAX12554: Functional Diagram Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .

Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.