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1.8V, 12-Bit, 250Msps ADC for Broadband Applications

Industry's Highest SNR and SFDR at High Input Frequencies

Product Details

Key Features

Simplified Block Diagram

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Key Features

  • 250Msps Conversion Rate
  • Excellent Low-Noise Characteristics
    • SNR = 66.7dB at fIN = 100MHz
    • SNR = 65.6dB at fIN = 250MHz
  • Excellent Dynamic Range
    • SFDR = 84.7dBc at fIN = 100MHz
    • SFDR = 80dBc at fIN = 250MHz
  • Single 1.8V Supply
  • 886mW Power Dissipation at fSAMPLE = 250Msps and fIN = 100MHz
  • On-Chip Track-and-Hold Amplifier
  • Internal 1.25V-Bandgap Reference
  • On-Chip Selectable Divide-by-2 Clock Input
  • LVDS Digital Outputs with Data Clock Output
  • MAX1215NEVKIT Available

Applications/Uses

  • Base-Station Power-Amplifier Linearization
  • Cable-Head End Receivers
  • Communications Test Equipment
  • Radar and Satellite Subsystems
  • Wireless and Wired Broadband Communications

Description

The MAX1215N is a monolithic, 12-bit, 250Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high-IF frequencies beyond 300MHz. The product operates with conversion rates up to 250Msps while consuming only 886mW.

At 250Msps and an input frequency of 100MHz, the MAX1215N achieves an 84.7dBc spurious-free dynamic range (SFDR) with excellent 66.7dB signal-to-noise ratio (SNR) that remains flat (within 2dB) for input tones up to 250MHz. This makes it ideal for wideband applications such as communications receivers, cable-head end receivers, and power-amplifier predistortion in cellular base-station transceivers (BTS).

The MAX1215N operates from a single 1.8V power supply. The analog input is designed for AC-coupled differential or single-ended operation. The ADC also features a selectable on-chip divide-by-2 clock circuit that accepts clock frequencies as high as 500MHz. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter provides LVDS-compatible digital outputs with data format selectable to be either two's complement or offset binary.

The MAX1215N is available in a 68-pin QFN package with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range.

See a parametric table of the complete family of pin-compatible, 8-/10-/12-bit high-speed ADCs.

Simplified Block Diagram

MAX1215N: Block Diagram MAX1215N: Block Diagram Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .