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1.8V, 12-Bit, 250Msps ADC for Broadband Applications

Product Details

Key Features

Applications/Uses

Simplified Block Diagram

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Key Features

  • 250Msps Conversion Rate
  • Low Noise Floor of -67.5dBFS
  • Excellent Low-Noise Characteristics
    • SNR = 65.5dB at fIN = 100MHz
    • SNR = 65dB at fIN = 250MHz
  • Excellent Dynamic Range
    • SFDR = 70.7dBc at fIN = 100MHz
    • SFDR = 72.4dBc at fIN = 250MHz
  • 65.4dB NPR for fNOTCH = 28.8MHz and a Noise Bandwidth of 50MHz
  • Single 1.8V Supply
  • 1006mW Power Dissipation at fSAMPLE = 250MHz and fIN = 100MHz
  • On-Chip Track-and-Hold Amplifier
  • Internal 1.24V-Bandgap Reference
  • On-Chip Selectable Divide-by-2 Clock Input
  • LVDS Digital Outputs with Data Clock Output
  • MAX1215 EV Kit Available

Applications/Uses

  • Base-Station Power-Amplifier Linearization
  • Cable-Head End Receivers
  • Communications Test Equipment
  • Radar and Satellite Subsystems
  • Wireless and Wired Broadband Communication

Description

The MAX1215 is a monolithic, 12-bit, 250Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high-IF frequencies up to 300MHz. The product operates with conversion rates up to 250Msps while consuming only 975mW.

At 250Msps and an input frequency up to 250MHz, the MAX1215 achieves a spurious-free dynamic range (SFDR) of 72.4dBc. Its excellent signal-to-noise ratio (SNR) of 66dB at 10MHz remains flat (within 2dB) for input tones up to 300MHz. This ADC yields an excellent low noise floor of -67.5dBFS, which makes it ideal for wideband applications such as cable-head end receivers and power-amplifier predistortion in cellular base-station transceivers.

The MAX1215 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 340MHz. This helps to reduce the phase noise of the input clock source. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible and the data format can be selected to be either two's complement or offset binary.

The MAX1215 is available in a 68-pin QFN package with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range.


New Unbuffered Version Available with Higher Dynamic Performance (MAX1215N)

See a parametric table of the complete family of pin-compatible, 8-/10-/12-bit high-speed ADCs.

Simplified Block Diagram

MAX1215: Block Diagram MAX1215: Block Diagram Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .