At 210Msps and an input frequency up to 250MHz, the MAX1214 achieves a spurious-free dynamic range (SFDR) of 77.2dBc. Its excellent signal-to-noise ratio (SNR) of 66dB at 10MHz remains flat (within 2dB) for input tones up to 300MHz. This ADC yields an excellent low noise floor of -67.6dBFS, which makes it ideal for wideband applications such as cable-head end receivers and power-amplifier predistortion in cellular base-station transceivers.
The MAX1214 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 340MHz. This helps to reduce the phase noise of the input clock source. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible and the data format can be selected to be either two's complement or offset binary.
The MAX1214 is available in a 68-pin QFN package with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range.
New Unbuffered Version Available with Higher Dynamic Performance (MAX1214N)
See a parametric table of the complete family of pin-compatible, 8-/10-/12-bit high-speed ADCs.
|Device||Fab Process||Technology||Sample size||Rejects||FIT at 25°C||FIT at 55°C|
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