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1.8V, Low-Power, 12-Bit, 170Msps ADC for Broadband Applications

Pin-Compatible Family of 170Msps to 250Msps, 12-/10-/8-Bit ADCs with the Industry's Best Dynamic Performance

Product Details

Key Features

Applications/Uses

Simplified Block Diagram

Technical Docs

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Key Features

  • 170Msps Conversion Rate
  • Excellent Low-Noise Characteristics
    • SNR = 67.2dB at fIN = 100MHz
    • SNR = 65.2dB at fIN = 250MHz
  • Excellent Dynamic Range
    • SFDR = 87dBc at fIN = 100MHz
    • SFDR = 79dBc at fIN = 250MHz
  • Single 1.8V Supply
  • 720mW Power Dissipation at fSAMPLE = 170Msps and fIN = 100MHz
  • On-Chip Track-and-Hold Amplifier
  • Internal 1.24V-Bandgap Reference
  • On-Chip Selectable Divide-by-2 Clock Input
  • LVDS Digital Outputs with Data Clock Output
  • MAX1213NEVKIT Available

Applications/Uses

  • Base-Station Power-Amplifier Linearization
  • Cable-Head End Receivers
  • Communications Test Equipment
  • Radar and Satellite Subsystems
  • Wireless and Wired Broadband Communications

Description

The MAX1213N is a monolithic, 12-bit, 170Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high-IF frequencies beyond 300MHz. The product operates with conversion rates up to 170Msps while consuming only 720mW.

At 170Msps and an input frequency up to 100MHz, the MAX1213N achieves an 87dBc spurious-free dynamic range (SFDR) with excellent 67.2dB signal-to-noise ratio (SNR) that remains flat (within 2dB) for input tones up to 250MHz. This makes it ideal for wideband applications such as communications receivers, cable-head end receivers, and power-amplifier predistortion in cellular base-station transceivers.

The MAX1213N operates from a single 1.8V power supply. The analog input is designed for AC-coupled differential or single-ended operation. The ADC also features a selectable on-chip divide-by-2 clock circuit that accepts clock frequencies as high as 340MHz. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter provides LVDS-compatible digital outputs with data format selectable to be either two's complement or offset binary.

The MAX1213N is available in a 68-pin QFN package with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range.

See a parametric table of the complete family of pin-compatible, 8-/10-/12-bit high-speed ADCs.

Simplified Block Diagram

MAX1213N: Block Diagram MAX1213N: Block Diagram Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .