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1.8V, 12-Bit, 170Msps ADC for Broadband Applications

Pin-Compatible Family of 170Msps-to-250Msps, 12-/10-/8-Bit ADCs with the Industry's Best Dynamic Performance

Product Details

Key Features

Applications/Uses

Simplified Block Diagram

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Key Features

  • 170Msps Conversion Rate
  • Low Noise Floor of -68dBFS
  • Excellent Low-Noise Characteristics
    • SNR = 65.8dB at fIN = 100MHz
    • SNR = 64.5dB at fIN = 250MHz
  • Excellent Dynamic Range
    • SFDR = 74dBc at fIN = 100MHz
    • SFDR = 72.9dBc at fIN = 250MHz
  • 59.5dB NPR for fNOTCH = 28.8MHz and a Noise Bandwidth of 50MHz
  • Single 1.8V Supply
  • 788mW Power Dissipation at fSAMPLE = 170MHz and fIN = 65MHz
  • On-Chip Track-and-Hold Amplifier
  • Internal 1.23V-Bandgap Reference
  • On-Chip Selectable Divide-by-2 Clock Input
  • LVDS Digital Outputs with Data Clock Output
  • MAX1213 EV Kit Available

Applications/Uses

  • Base-Station Power-Amplifier Linearization
  • Cable Head-End Receivers
  • Communications Test Equipment
  • Radar and Satellite Subsystems
  • Wireless and Wired Broadband Communication

Description

The MAX1213 is a monolithic, 12-bit, 170Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high-IF frequencies up to 300MHz. The product operates with conversion rates up to 170Msps while consuming only 788mW.

At 170Msps and an input frequency up to 250MHz, the MAX1213 achieves a spurious-free dynamic range (SFDR) of 72.9dBc. Its excellent signal-to-noise ratio (SNR) of 66.2dB at 10MHz remains flat (within 2dB) for input tones up to 250MHz. This ADC yields an excellent low-noise floor of -68dBFS, which makes it ideal for wideband applications such as cable head-end receivers and power-amplifier predistortion in cellular base-station transceivers.

The MAX1213 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 340MHz. This helps to reduce the phase noise of the input clock source. A low-voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible and the data format can be selected to be either two's complement or offset binary.

The MAX1213 is available in a 68-pin QFN package with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range.

See the Pin-Compatible Versions table in the full data sheet for a complete selection of 8-bit, 10-bit, and 12-bit high-speed ADCs in this family (with and without input buffers).

Simplified Block Diagram

MAX1213: Block Diagram MAX1213: Block Diagram Zoom icon

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .