Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
DescriptionThe MAX1198 is a 3.3V, dual, 8-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving two ADCs. The MAX1198 is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumentation, and digital communications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 264mW, while delivering a typical signal-to-noise and distortion (SINAD) of 48.1dB at an input frequency of 50MHz and a sampling rate of 100Msps. The T/H-driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1198 features a 3.2mA sleep mode, as well as a 0.15µA power-down mode to conserve power during idle periods.
An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired, for applications requiring increased accuracy or a different input voltage range.
The MAX1198 features parallel, CMOS-compatible three-state outputs. The digital output format can be set to two's complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing with various logic families. The MAX1198 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range.
See a parametric table of the complete family of pin-compatible, 8-bit high-speed ADCs.
For a 10-bit, pin-compatible upgrade, refer to the MAX1180 data sheet. With the N.C. pins of the MAX1198 internally pulled down to ground, this ADC becomes a drop-in replacement for the MAX1180.
- Single 2.7V to 3.6V Operation
- Excellent Dynamic Performance
- 48.1dB/47.6dB SINAD at fIN = 50MHz/200MHz
- 66dBc/61.5dBc SFDR at fIN = 50MHz/200MHz
- -72dB Interchannel Crosstalk at fIN = 50MHz
- Low Power
- 264mW (Normal Operation)
- 10.6mW (Sleep Mode)
- 0.5µW (Shutdown Mode)
- 0.05dB Gain and ±0.1° Phase Matching
- Wide ±1VP-P Differential Analog Input Voltage Range
- 400MHz -3dB Input Bandwidth
- On-Chip 2.048V Precision Bandgap Reference
- User-Selectable Output Format—Two's Complement or Offset Binary
- Pin-Compatible 8-Bit and 10-Bit Upgrades Available
- Baseband I/Q Sampling
- Battery-Powered Applications
- MMDS Modems
- Multichannel IF Sampling
- Set-Top Boxes
- Ultrasound and Medical Imaging
- VSAT Terminals
- WLAN, WWAN, WLL,
|Part Number||Input Chan.||Resolution|
|Full Pwr. BW|
|Data Bus Interface||Package/Pins||Budgetary|
|max ≥||min||min||See Notes|
MAX1198EVKIT: Evaluation Kit for the MAX1195, MAX1196, MAX1197, and MAX1198
Technical DocumentsTutorial 4294 Differential Gain and Phase—Why Measure It, if You Cannot See It?
App Note 3190 Coherent Sampling Calculator (CSC)
Tutorial 1819 Selecting the Optimum Test Tones and Test Equipment for Successful High-Speed ADC Sinewave Testing
Tutorial 1040 Coherent Sampling vs. Window Sampling
Tutorial 729 Dynamic Testing of High-Speed ADCs, Part 2
Tutorial 728 Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1
Tools & Models
|Device||Fab Process||Technology||Sample size||Rejects||FIT at 25°C||FIT at 55°C||Material Composition|
|Tutorial||4294||Differential Gain and Phase—Why Measure It, if You Cannot See It?|
|App Note||3190||Coherent Sampling Calculator (CSC)|
|Tutorial||1819||Selecting the Optimum Test Tones and Test Equipment for Successful High-Speed ADC Sinewave Testing|
|Tutorial||1040||Coherent Sampling vs. Window Sampling|
|Tutorial||729||Dynamic Testing of High-Speed ADCs, Part 2|
|Tutorial||728||Defining and Testing Dynamic Parameters in High-Speed ADCs, Part 1|