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Dual 10-Bit, 80Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs

Product Details

Key Features

Parametric specs for High-Speed ADCs (> 5Msps)
Resolution (bits) 10
# Input Channels 2
Sample Rate (Msps) (max) 80
Data Bus Interface µP/10
AC Specs (MHz) (@ fIN) 20
SFDR (dBc) (min) 73
ENOB (bits) (min) 9.43
SINAD (dB) 58.5
SNR (dB) 59
THD (dB) -70
DNL (±LSB) 1
INL (±LSB) 2.2
Package/Pins TQFP/48
Budgetary
Price (See Notes)
15.71
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Simplified Block Diagram

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Parameters

Parametric specs for High-Speed ADCs (> 5Msps)
Resolution (bits) 10
# Input Channels 2
Sample Rate (Msps) (max) 80
Data Bus Interface µP/10
AC Specs (MHz) (@ fIN) 20
SFDR (dBc) (min) 73
ENOB (bits) (min) 9.43
SINAD (dB) 58.5
SNR (dB) 59
THD (dB) -70
DNL (±LSB) 1
INL (±LSB) 2.2
Package/Pins TQFP/48
Budgetary
Price (See Notes)
15.71

Key Features

  • Single 3V Operation
  • Excellent Dynamic Performance
    • 59dB SNR at fIN = 20MHz
    • 73dB SFDR at fIN = 20MHz
  • Low Power
    • 82mA (Normal Operation)
    • 2.8mA (Sleep Mode)
    • 1µA (Shutdown Mode)
  • 0.02dB Gain and 0.25° Phase Matching (typ)
  • Wide ±1VP-P Differential Analog Input Voltage Range
  • 400MHz, -3dB Input Bandwidth
  • On-Chip 2.048V Precision Bandgap Reference
  • User-Selectable Output Format—Two's Complement or Offset Binary
  • 48-Pin TQFP Package with Exposed Pad for Improved Thermal Dissipation
  • Evaluation Kit Available

Applications/Uses

  • High-Resolution Imaging
  • I/Q Channel Digitization
  • Instrumentation
  • Multichannel IF Undersampling
  • Video Application

Description

The MAX1181 is a 3V, dual 10-bit, analog-to-digital converter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving two pipelined, nine-stage ADCs. The MAX1181 is optimized for low-power, high-dynamic performance applications in imaging, instrumentation, and digital communication applications. The MAX1181 operates from a single 2.7V to 3.6V supply, consuming only 246mW, while delivering a typical signal-to-noise ratio (SNR) of 59dB at an input frequency of 20MHz and a sampling rate of 80Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1181 features a 2.8mA sleep mode, as well as a 1µA power-down mode to conserve power during idle periods.

An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of the internal or external reference, if desired for applications requiring increased accuracy or a different input voltage range.

The MAX1181 features parallel, CMOS-compatible three-state outputs. The digital output format is set to two's complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing. The MAX1181 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range.

Pin-compatible higher and lower speed versions of the MAX1181 are also available. Please refer to the MAX1180 data sheet for 105Msps, the MAX1182 data sheet for 65Msps, the MAX1183 data sheet for 40Msps, and the MAX1184 data sheet for 20Msps. In addition to these speed grades, this family includes a 20Msps multiplexed output version (MAX1185), for which digital data is presented time-interleaved on a single, parallel 10-bit output port.

Simplified Block Diagram

MAX1181: Functional Diagram MAX1181: Functional Diagram Zoom icon

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .