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24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA, Delta-Sigma ADC with I2C Interface

24-Bit Delta-Sigma ADC Offers the most integrated solution for Force Sense

Product Details

Key Features

Parametric specs for Precision ADCs (< 5Msps)
Resolution (bits) (ADC) 24
# Input Channels 6
Conv. Rate (ksps) (max) 16
Data Bus I2C
ADC Architecture Sigma-Delta
Diff/S.E. Input Both
External VREF (V) (min) 1.5
External VREF (V) (max) 3.6
Package/Pins THIN WLP/36
Budgetary
Price (See Notes)
5.68
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Simplified Block Diagram

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Parameters

Parametric specs for Precision ADCs (<u><</u> 5Msps)
Resolution (bits) (ADC) 24
# Input Channels 6
Conv. Rate (ksps) (max) 16
Data Bus I2C
ADC Architecture Sigma-Delta
Diff/S.E. Input Both
External VREF (V) (min) 1.5
External VREF (V) (max) 3.6
Package/Pins THIN WLP/36
Budgetary
Price (See Notes)
5.68

Key Features

  • Analog Supply
    • 2.7V to 3.6V
  • Digital Supply
    • Internal LDO Disabled—1.7V to 2.0V
    • Internal LDO Enabled—2.0V to 3.6V
  • 3ppm INL (typ)
  • PGA
    • Gains of 1, 2, 4, 8, 16, 32, 64, 128
    • Low-Noise Mode, 6.2nV/ Noise
    • Low-Power Mode, 10nV/ Noise
  • Input-Referred Noise
    • PGA Low-Noise Mode, Gain of 64 at 1ksps Continuous, 0.15μVRMS
  • Fully Differential Signal and Reference Inputs
  • Internal System Clock of 8.192MHz
  • I2C-Compatible Serial Interface
  • Supports Standard, Fast-Mode, and Fast-Mode Plus I2C Specifications
  • 64-Entry On-Chip FIFO
  • Hardware Interrupt for Input Monitoring and FIFO Usage
  • On-Demand Self and System Gain and Offset Calibration
  • User-Programmable Offset and Gain Registers
  • Two Power-Down Modes (SLEEP and STANDBY)
  • Low Power Dissipation
  • ESD Rating: ±2.5kV (HBM), 750V (CDM)
  • -40°C to +85°C Operating Temperature Range
  • 6 x 6 Bump, 0.4mm Pitch, 2.838mm x 2.838mm x 0.5mm WLP

Applications/Uses

  • Battery-Powered Instrumentation
  • Medical Equipment
  • Pressure Sensors
  • Wearable Electronics
  • Weigh Scales

Description

The MAX11261 is a 6-channel, 24-bit delta-sigma ADC that achieves exceptional performance while consuming very low power. Sample rates up to 16ksps allow precision DC measurements. The device also features a 64-entry, on-chip FIFO to offload the host processor. The MAX11261 communicates through an I2C-compatible serial interface and is available in a small, wafer-level package (WLP).

The MAX11261 offers a 6.2nV/ noise programmable gain amplifier (PGA) with gain settings from 1x to 128x. The integrated PGA provides isolation of the signal inputs from the switched capacitor sampling network. The PGA also enables the MAX11261 to interface directly with high-impedance sources without compromising the available dynamic range.

The MAX11261 operates from a single 2.7V to 3.6V analog supply. The digital supply range is 1.7V to 2.0V (internal LDO off) and 2.0V to 3.6V (internal LDO on) enabling communication with 1.8V, 2.5V, 3V, or 3.3V logic.

Simplified Block Diagram

MAX11261: Functional Diagram MAX11261: Functional Diagram Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .