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Quad, 12-Bit, 40Msps, 1.8V ADC with Serial LVDS Outputs

40Msps to 65Msps, Quad, 12-Bit LVDS ADC Family Offers the Lowest Power

Product Details

Key Features

Parametric specs for High-Speed ADCs (> 5Msps)
Resolution (bits) 12
# Input Channels 4
Sample Rate (Msps) (max) 40
Data Bus Interface LVDS
Serial
AC Specs (MHz) (@ fIN) 19.3
SFDR (dBc) (min) 89
ENOB (bits) (min) 11.3
SINAD (dB) 69.1
SNR (dB) 69.2
THD (dB) -88.7
DNL (±LSB) 0.25
INL (±LSB) 0.4
Package/Pins QFN/68
Budgetary
Price (See Notes)
61.7
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Simplified Block Diagram

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Parameters

Parametric specs for High-Speed ADCs (> 5Msps)
Resolution (bits) 12
# Input Channels 4
Sample Rate (Msps) (max) 40
Data Bus Interface LVDS
Serial
AC Specs (MHz) (@ fIN) 19.3
SFDR (dBc) (min) 89
ENOB (bits) (min) 11.3
SINAD (dB) 69.1
SNR (dB) 69.2
THD (dB) -88.7
DNL (±LSB) 0.25
INL (±LSB) 0.4
Package/Pins QFN/68
Budgetary
Price (See Notes)
61.7

Key Features

  • Four ADC Channels with Serial LVDS/SLVS Outputs
  • Excellent Dynamic Performance
    • 69.9dB SNR at fIN = 5.3MHz
    • 93.7dBc SFDR at fIN = 5.3MHz
    • -90dB Channel Isolation
  • Ultra-Low Power
    • 135mW per Channel (Normal Operation)
    • 1.5mW Total (Shutdown Mode)
  • Accepts 20% to 80% Clock Duty Cycle
  • Self-Aligning Data-Clock to Data-Output Interface
  • Fully Differential Analog Inputs
  • Wide ±1.4VP-P Differential Input Voltage Range
  • Internal/External Reference Option
  • Test Mode for Digital Signal Integrity
  • LVDS Outputs Support Up to 30in FR-4 Backplane Connections
  • Small, 68-Pin QFN with Exposed Paddle
  • Evaluation Kit Available (MAX1127EVKIT)

Applications/Uses

  • Instrumentation
  • Multichannel Communication Systems
  • Positron Emission Tomography (PET) Imaging
  • Ultrasound and Medical Imaging

Description

The MAX1126 quad, 12-bit analog-to-digital converter (ADC) features fully differential inputs, a pipelined architecture, and digital error correction. This ADC is optimized for low-power, high-dynamic performance for medical imaging, communications, and instrumentation applications. The MAX1126 operates from a 1.7V to 1.9V single supply and consumes only 563mW while delivering a 69.9dB signal-to-noise ratio (SNR) at a 5.3MHz input frequency. In addition to low operating power, the MAX1126 features an 813µA power-down mode for idle periods.

An internal 1.24V precision bandgap reference sets the ADC's full-scale range. A flexible reference structure allows the use of an external reference for applications requiring increased accuracy or a different input voltage range.

A single-ended clock controls the conversion process. An internal duty-cycle equalizer allows for wide variations in input-clock duty cycle. An on-chip phase-locked loop (PLL) generates the high-speed serial low-voltage differential signaling (LVDS) clock.

The MAX1126 provides serial LVDS outputs for data, clock, and frame alignment signals. The output data is presented in two's complement or binary format.

Refer to the MAX1127 data sheet for a pin-compatible 65Msps version of the MAX1126.

The MAX1126 is available in a small, 10mm x 10mm x 0.9mm, 68-pin QFN package with exposed paddle and is specified for the extended industrial (-40°C to +85°C) temperature range.

Simplified Block Diagram

MAX1126: Functional Diagram MAX1126: Functional Diagram Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .

Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.