MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
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Key Features
Applications/Uses
| Resolution (bits) | 10 |
| # Input Channels | 1 |
| Sample Rate (Msps) (max) | 250 |
| Data Bus Interface | µP/10 LVDS |
| AC Specs (MHz) (@ fIN) | 180 |
| SFDR (dBc) (min) | 68.3 |
| SINAD (dB) | 56 |
| SNR (dB) | 56.3 |
| DNL (±LSB) | 0.5 |
| INL (±LSB) | 0.8 |
| Package/Pins | QFN/68 |
| Budgetary Price (See Notes) | 91.26 |
Simplified Block Diagram
Technical Docs
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Sampling:
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Parameters
| Resolution (bits) | 10 |
| # Input Channels | 1 |
| Sample Rate (Msps) (max) | 250 |
| Data Bus Interface | µP/10 LVDS |
| AC Specs (MHz) (@ fIN) | 180 |
| SFDR (dBc) (min) | 68.3 |
| SINAD (dB) | 56 |
| SNR (dB) | 56.3 |
| DNL (±LSB) | 0.5 |
| INL (±LSB) | 0.8 |
| Package/Pins | QFN/68 |
| Budgetary Price (See Notes) | 91.26 |
Key Features
- 250Msps Conversion Rate
- SNR = 56.8dB/55.5dB at fIN = 100MHz/500MHz
- SFDR = 71dBc/63.8dBc at fIN = 100MHz/500MHz
- NPR = 54.8dB at fNOTCH = 28.8MHz
- Single 1.8V Supply
- 477mW Power Dissipation at 250Msps
- On-Chip Track-and-Hold and Internal Reference
- On-Chip Selectable Divide-by-2 Clock Input
- LVDS Digital Outputs with Data Clock Output
- Evaluation Kit Available (Order MAX1124EVKIT)
Applications/Uses
- Cable-Head End Systems
- Communications Test Equipment
- Digital Predistortion Receivers
- Radar and Satellite Subsystems Antenna Array Processing
- Wireless and Wired Broadband Communication
Description
At 250Msps and an input frequency of 100MHz, the MAX1124 achieves a spurious-free dynamic range (SFDR) of 71dBc. Its excellent signal-to-noise ratio (SNR) of 57.1dB at 10MHz remains flat (within 1dB) for input tones up to 500MHz. This makes the MAX1124 ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems.
The MAX1124 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 500MHz. This helps to reduce the phase noise of the input clock source. A differential LVDS sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible, and the data format can be selected to be either two's complement or offset binary.
The MAX1124 is available in a 68-pin QFN with exposed pad (EP) and is specified over the industrial (-40°C to +85°C) temperature range.
For pin-compatible, lower speed versions of the MAX1124, refer to the MAX1122 (170Msps) and the MAX1123 (210Msps) data sheets. For a pin-compatible 8-bit version of the MAX1124, refer to the MAX1121 data sheet.
See a parametric table of the complete family of pin-compatible, 8-/10-/12-bit high-speed ADCs.
Technical Docs
Support & Training
Search our knowledge base for answers to your technical questions.
Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .
Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.
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