The MAX1124 is a monolithic 10-bit, 250Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high IF frequencies up to 500MHz. The product operates with conversion rates of up to 250Msps while consuming only 477mW.

At 250Msps and an input frequency of 100MHz, the MAX1124 achieves a spurious-free dynamic range (SFDR) of 71dBc. Its excellent signal-to-noise ratio (SNR) of 57.1dB at 10MHz remains flat (within 1dB) for input tones up to 500MHz. This makes the MAX1124 ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems.

The MAX1124 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 500MHz. This helps to reduce the phase noise of the input clock source. A differential LVDS sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible, and the data format can be selected to be either two's complement or offset binary.

The MAX1124 is available in a 68-pin QFN with exposed pad (EP) and is specified over the industrial (-40°C to +85°C) temperature range.

For pin-compatible, lower speed versions of the MAX1124, refer to the MAX1122 (170Msps) and the MAX1123 (210Msps) data sheets. For a pin-compatible 8-bit version of the MAX1124, refer to the MAX1121 data sheet.

See a parametric table of the complete family of pin-compatible, 8-/10-/12-bit high-speed ADCs.

MAX1124: Block Diagram

Enlarge+

Key Features

250Msps Conversion Rate
SNR = 56.8dB/55.5dB at f_IN = 100MHz/500MHz
SFDR = 71dBc/63.8dBc at f_IN = 100MHz/500MHz
NPR = 54.8dB at f_NOTCH = 28.8MHz
Single 1.8V Supply
477mW Power Dissipation at 250Msps
On-Chip Track-and-Hold and Internal Reference
On-Chip Selectable Divide-by-2 Clock Input
LVDS Digital Outputs with Data Clock Output
Evaluation Kit Available (Order MAX1124EVKIT)

Applications/Uses

Cable-Head End Systems
Communications Test Equipment
Digital Predistortion Receivers
Radar and Satellite Subsystems Antenna Array Processing
Wireless and Wired Broadband Communication

Key Specs

Part Number

Input Chan.

Resolution
(bits)

Sample Rate
(Msps)

AC Specs
(MHz)

SFDR
(dBc)

SINAD
(dB)

SNR
(dB)

DNL
(±LSB)

INL
(±LSB)

Full Pwr. BW
(MHz)

I_CC
(mA)

Data Bus Interface

Package/Pins

Budgetary
Price

max ≥

@ f_IN

min

typ

See Notes

MAX1124

250

180

68.3

56.3

0.5

0.8

600

265

µP/10

LVDS

QFN/68

$55.74 @1k

See All High-Speed ADCs (> 5Msps) (73)

Pricing Notes:

This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific and version-specific prices and delivery, please see the price and availability page or contact an authorized distributor.

Design Resources

MAX1124EVKIT: Evaluation Kit for the MAX1121, MAX1122, MAX1123, and MAX1124

Technical Documents

App Note 3557 "Stitch" Your Way Out of Logic-Analyzer Memory Limitations
App Note 3495 Combine Multiple Data Files to Optimize INL/DNL Processing
App Note 3228 Improving Gain Flatness without Sacrificing Dynamic Performance in High-IF ADCs
App Note 3190 Coherent Sampling Calculator (CSC)
App Note 2884 Secondary-Side Transformer Termination Improves Gain Flatness in High-Speed ADCs

Quality and Environmental Data

Request Reliability Report for: MAX1124
Lead-Free Package Tin (Sn) Whisker Reports

Order

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Technical Docs

Type	ID	Title
App Note	3557	"Stitch" Your Way Out of Logic-Analyzer Memory Limitations
App Note	3495	Combine Multiple Data Files to Optimize INL/DNL Processing
App Note	3228	Improving Gain Flatness without Sacrificing Dynamic Performance in High-IF ADCs
App Note	3190	Coherent Sampling Calculator (CSC)
App Note	2884	Secondary-Side Transformer Termination Improves Gain Flatness in High-Speed ADCs