1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
DescriptionThe MAX1124 is a monolithic 10-bit, 250Msps analog-to-digital converter (ADC) optimized for outstanding dynamic performance at high IF frequencies up to 500MHz. The product operates with conversion rates of up to 250Msps while consuming only 477mW.
At 250Msps and an input frequency of 100MHz, the MAX1124 achieves a spurious-free dynamic range (SFDR) of 71dBc. Its excellent signal-to-noise ratio (SNR) of 57.1dB at 10MHz remains flat (within 1dB) for input tones up to 500MHz. This makes the MAX1124 ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems.
The MAX1124 requires a single 1.8V supply. The analog input is designed for either differential or single-ended operation and can be AC- or DC-coupled. The ADC also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 500MHz. This helps to reduce the phase noise of the input clock source. A differential LVDS sampling clock is recommended for best performance. The converter's digital outputs are LVDS compatible, and the data format can be selected to be either two's complement or offset binary.
The MAX1124 is available in a 68-pin QFN with exposed pad (EP) and is specified over the industrial (-40°C to +85°C) temperature range.
For pin-compatible, lower speed versions of the MAX1124, refer to the MAX1122 (170Msps) and the MAX1123 (210Msps) data sheets. For a pin-compatible 8-bit version of the MAX1124, refer to the MAX1121 data sheet.
See a parametric table of the complete family of pin-compatible, 8-/10-/12-bit high-speed ADCs.
- 250Msps Conversion Rate
- SNR = 56.8dB/55.5dB at fIN = 100MHz/500MHz
- SFDR = 71dBc/63.8dBc at fIN = 100MHz/500MHz
- NPR = 54.8dB at fNOTCH = 28.8MHz
- Single 1.8V Supply
- 477mW Power Dissipation at 250Msps
- On-Chip Track-and-Hold and Internal Reference
- On-Chip Selectable Divide-by-2 Clock Input
- LVDS Digital Outputs with Data Clock Output
- Evaluation Kit Available (Order MAX1124EVKIT)
- Cable-Head End Systems
- Communications Test Equipment
- Digital Predistortion Receivers
- Radar and Satellite Subsystems Antenna Array Processing
- Wireless and Wired Broadband Communication
|Part Number||Input Channels||Resolution|
|Full Pwr. BW|
|Data Bus Interface||Package/Pins||Budgetary|
|max||@ fIN||min||min||typ||See Notes|
MAX1124EVKIT: Evaluation Kit for the MAX1121, MAX1122, MAX1123, and MAX1124
Technical DocumentsApp Note 3557 "Stitch" Your Way Out of Logic-Analyzer Memory Limitations
App Note 3495 Combine Multiple Data Files to Optimize INL/DNL Processing
App Note 3228 Improving Gain Flatness without Sacrificing Dynamic Performance in High-IF ADCs
App Note 3190 Coherent Sampling Calculator (CSC)
App Note 2884 Secondary-Side Transformer Termination Improves Gain Flatness in High-Speed ADCs
|Device||Fab Process||Technology||Sample size||Rejects||FIT at 25°C||FIT at 55°C||Material Composition|
|App Note||3557||"Stitch" Your Way Out of Logic-Analyzer Memory Limitations|
|App Note||3495||Combine Multiple Data Files to Optimize INL/DNL Processing|
|App Note||3228||Improving Gain Flatness without Sacrificing Dynamic Performance in High-IF ADCs|
|App Note||3190||Coherent Sampling Calculator (CSC)|
|App Note||2884||Secondary-Side Transformer Termination Improves Gain Flatness in High-Speed ADCs|