±5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
DescriptionThe MAX106 PECL-compatible, 600Msps, 8-bit analog-to-digital converter (ADC) allows accurate digitizing of analog signals with bandwidths to 2.2GHz. Fabricated on Maxim's proprietary advanced GST-2 bipolar process, the MAX106 integrates a high-performance track/hold (T/H) amplifier and a quantizer on a single monolithic die.
The innovative design of the internal T/H, which has an exceptionally wide 2.2GHz full-power input bandwidth, results in high, 7.6 effective bits performance at the Nyquist frequency. A fully differential comparator design and decoding circuitry combine to reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastable performance of one error per 1027 clock cycles. Unlike other ADCs, which can have errors that result in false full- or zero-scale outputs, the MAX106 limits the error magnitude to 1LSB.
The analog input is designed for either differential or single-ended use with a ±250mV input voltage range. Dual, differential, PECL-compatible output data paths ensure easy interfacing and include an 8:16 demultiplexer feature that reduces output data rates to one-half the sampling clock rate. The PECL outputs can be operated from any supply between +3V to +5V for compatibility with +3.3V or +5V referenced systems. Control inputs are provided for interleaving additional MAX106 devices to increase the effective system sampling rate.
The MAX106 is packaged in a 25mm x 25mm, 192-contact Enhanced Super-Ball-Grid Array (ESBGA™), and is specified over the commercial (0°C to +70°C) temperature range. For a pin-compatible higher speed upgrade, refer to the MAX104 (1Gsps) and MAX108 (1.5Gsps) data sheets.
- 600Msps Conversion Rate
- 2.2GHz Full-Power Analog Input Bandwidth
- 7.6 Effective Bits at fIN = 300MHz (Nyquist frequency)
- ±0.25LSB INL and DNL
- 50Ω Differential Analog Inputs
- ±250mV Input Signal Range
- On-Chip, +2.5V Precision Bandgap Voltage Reference
- Latched, Differential PECL Digital Outputs
- Low Error Rate: 10-27 Metastable States
- Selectable 8:16 Demultiplexer
- Internal Demux Reset Input with Reset Output
- 192-Contact ESBGA
- Pin Compatible with Faster MAX104/MAX108
- Digital Oscilloscopes
- Digital RF/IF Signal Processing
- High-Speed Data Acquisition
- Radar/ECM Systems
Technical DocumentsTutorial 810 Understanding Flash ADCs
Tutorial 800 Design a Low-Jitter Clock for High-Speed Data Converters
App Note 642 ADC Captures 1Gsps
Tutorial 283 INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs)
|Device||Fab Process||Technology||Sample size||Rejects||FIT at 25°C||FIT at 55°C||Material Composition|
|Tutorial||810||Understanding Flash ADCs|
|Tutorial||800||Design a Low-Jitter Clock for High-Speed Data Converters|
|App Note||642||ADC Captures 1Gsps|
|Tutorial||283||INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs)|