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Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier

Product Details

Key Features

Parametric specs for High-Speed ADCs (> 5Msps)
Resolution (bits) 6
# Input Channels 2
Sample Rate (Msps) (max) 800
Data Bus Interface µP/8
Demuxed
LVPECL
AC Specs (MHz) (@ fIN) 200
SFDR (dBc) (min) 45
ENOB (bits) (min) 5.8
SINAD (dB) 36.4
SNR (dB) 37
THD (dB) -44.5
DNL (±LSB) 0.25
INL (±LSB) 0.2
Package/Pins TQFP/80
Budgetary
Price (See Notes)
45.22
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Simplified Block Diagram

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Parameters

Parametric specs for High-Speed ADCs (> 5Msps)
Resolution (bits) 6
# Input Channels 2
Sample Rate (Msps) (max) 800
Data Bus Interface µP/8
Demuxed
LVPECL
AC Specs (MHz) (@ fIN) 200
SFDR (dBc) (min) 45
ENOB (bits) (min) 5.8
SINAD (dB) 36.4
SNR (dB) 37
THD (dB) -44.5
DNL (±LSB) 0.25
INL (±LSB) 0.2
Package/Pins TQFP/80
Budgetary
Price (See Notes)
45.22

Key Features

  • Two Matched 6-Bit, 800Msps ADCs
  • Excellent Dynamic Performance
    • 36.4dB SINAD at fIN ≈ 200MHz and
    • fCLK ≈ 800MHz
  • Typical INL and DNL: ±0.25 LSB
  • Channel-to-Channel Phase Matching: ±0.2°
  • Channel-to-Channel Gain Matching: ±0.04dB
  • 6:12 Demultiplexer reduces the Data Rates to 400MHz
  • Low Error Rate: 1016 Metastable States at 800Msps
  • LVDS Digital Outputs in Two's Complement Format

Applications/Uses

  • Communication Systems
  • Test Instrumentation
  • VSAT Receivers
  • Wireless Local Area Networks (WLANs)

Description

The MAX105 is a dual, 6-bit, analog-to-digital converter (ADC) designed to allow fast and precise digitizing of in-phase (I) and quadrature (Q) baseband signals. The MAX105 converts the analog signals of both I and Q components to digital outputs at 800Msps while achieving a signal-to-noise ratio (SNR) of typically 37dB with an input frequency of 200MHz, and an integral nonlinearity (INL) and differential nonlinearity (DNL) of ±0.25 LSB. The MAX105 analog input preamplifiers feature a 400MHz, -0.5dB, and a 1.5GHz, -3dB analog input bandwidth. Matching channel-to-channel performance is typically 0.04dB gain, 0.1 LSB offset, and 0.2 degrees phase. Dynamic performance is 36.4dB signal-to-noise plus distortion (SINAD) with a 200MHz analog input signal and a sampling speed of 800MHz. A fully differential comparator design and encoding circuits reduce out-of-sequence errors, and ensure excellent metastable performance of only one error per 1016 clock cycles.

In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two's complement format. The MAX105 operates from a +5V analog supply and the LVDS output ports operate at +3.3V. The data converter's typical power dissipation is 2.6W. The device is packaged in an 80-pin, TQFP package with exposed paddle, and is specified for the extended (-40° C to +85°C) temperature range. For a lower-speed, 400Msps version of the MAX105, please refer to the MAX107 data sheet.

Simplified Block Diagram

MAX105: Pin Configuration MAX105: Pin Configuration Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .

Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.