Simplified Block Diagram
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- 1Gsps Conversion Rate
- 2.2GHz Full-Power Analog Input Bandwidth
- > 7.5 Effective Bits at fIN = 500MHz (Nyquist Frequency)
- ±0.25 LSB INL and DNL
- 50Ω Differential Analog Inputs
- ±250mV Input Signal Range
- On-Chip, +2.5V Precision Bandgap Voltage Reference
- Latched, Differential PECL Digital Outputs
- Low Error Rate: 10-16 Metastable States at 1Gsps
- Selectable 8:16 Demultiplexer
- Internal Demux Reset Input with Reset Output
- 192-Contact ESBGA Package
- Automated Test Equipment (ATE)
- Digital Oscilloscopes
- Digital RF/IF Signal Processing
- Direct RF Downconversion
- High-Energy Physics
- High-Speed Data Acquisition
- Radar/Sonar/ECM Systems
The innovative design of the internal T/H, which has an exceptionally wide 2.2GHz full-power input bandwidth, results in high performance (greater than 7.5 effective bits) at the Nyquist frequency. A fully differential comparator design and decoding circuitry reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastable performance of one error per 1016 clock cycles. Unlike other ADCs that can have errors resulting in false full- or zero-scale outputs, the MAX104 limits the error magnitude to 1 LSB.
The analog input is designed for either differential or single-ended use with a ±250mV input voltage range. Dual, differential, PECL-compatible output data paths ensure easy interfacing and include an 8:16 demultiplexer feature that reduces output data rates to one-half the sampling clock rate. The PECL outputs can be operated from any supply between +3V to +5V for compatibility with +3.3V or +5V referenced systems. Control inputs are provided for interleaving additional MAX104 devices to increase the effective system sampling rate.
The MAX104 is packaged in a 25mm x 25mm, 192-contact Enhanced Super-Ball Grid Array (ESBGA™) and is specified over the commercial (0°C to +70°C) temperature range.