Ultra-Low-Power, High-Dynamic-Performance, 22Msps Analog Front End

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The MAX5864 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5864 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs' analog I-Q input amplifiers are fully differential and accept 1VP-P full-scale signals. Typical I-Q channel phase matching is ±0.1° and amplitude matching is ±0.03dB. The ADCs feature 48.5dB SINAD and 69dBc spurious-free dynamic range (SFDR) at fIN = 5.5MHz and fCLK = 22Msps. The DACs' analog I-Q outputs are fully differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase match is ±0.15° and amplitude match is ±0.05dB. The DACs also feature dual 10-bit resolution with 71.7dBc SFDR, and 57dB SNR at fOUT = 2.2MHz and fCLK = 22MHz.

The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 42mW at fCLK = 22Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5864 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5864 operates on a +2.7V to +3.3V analog power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 5.6mA in idle mode and 1µA in shutdown mode. The MAX5864 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin thin QFN package. See a parametric table of the complete family of pin-compatible AFEs.
MAX5864: Functional Diagram MAX5864: Functional Diagram Enlarge+

Key Features

  • Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs
  • Ultra-Low Power
    • 42mW at fCLK = 22MHz (Transceiver Mode)
    • 34mW at fCLK = 15.36MHz (Transceiver Mode)
    • Low-Current Idle and Shutdown Modes
  • Excellent Dynamic Performance
    • 48.5dB SINAD at fIN = 5.5MHz (ADC)
    • 71.7dB SFDR at fOUT = 2.2MHz (DAC)
  • Excellent Gain/Phase Match
    • ±0.1° Phase, ±0.03dB Gain at fIN = 5.5MHz (ADC)
  • Internal/External Reference Option
  • +1.8V to +3.3V Digital Output Level (TTL/CMOS Compatible)
  • Multiplexed Parallel Digital Input/Output for ADCs/DACs
  • Miniature 48-Pin Thin QFN Package (7mm x 7mm)
  • Evaluation Kit Available (Order MAX5865EVKIT)


  • 3G Wireless Terminals
  • Fixed/Mobile Broadband Wireless Modems
  • Narrowband/Wideband CDMA Handsets
  • PDAs

See parametric specs for Fast CODECs / Analog Front-End (AFE) (7)

Part NumberInput ChannelsConversion Speed
Output Chan.Speed
Noise Spectral Density
MAX5864 22248.6 @ 5.5MHz1022271.7 @ 2.2MHz-70 @ 2.2MHz-128.4 @ 2.2MHz
2.7 to 3.3
$5.93 @1k

Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific and version-specific prices and delivery, please see the price and availability page or contact an authorized distributor.

MAX5863EVKIT: Evaluation Kit for the MAX5863, MAX5864, and MAX5865
MAX5864EVKIT: Evaluation Kit for the MAX5863, MAX5864, and MAX5865
MAX5865EVKIT: Evaluation Kit for the MAX5863, MAX5864, and MAX5865
Request Reliability Report for: MAX5864 
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C   Material Composition  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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