Product Details
Key Features
Applications/Uses
# Input Channels (ADC) | 2 |
Conversion Speed (Msps) (ADC) | 22 |
SNR (dB) (@ fIN) | 48.6 @ 5.5MHz |
Resolution (bits) (DAC) | 10 |
Output Chan. (DAC) | 2 |
Speed (Msps) (DAC) | 22 |
SFDR (dBc) (@ fOUT) | 71.7 @ 2.2MHz |
THD (dBc) (@ fOUT) | -70 @ 2.2MHz |
Noise Spectral Density (dBFS/Hz) (@ fOUT) | -128.4 @ 2.2MHz |
VSUPPLY (V) | 1.8 2.7 to 3.3 |
Package/Pins | TQFN/48 |
Budgetary Price (See Notes) | 6.92 |
Simplified Block Diagram
Technical Docs
Data Sheet | Ultra-Low-Power, High-Dynamic-Performance, 22Msps Analog Front End | Nov 11, 2003 |
Support & Training
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Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .
Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.
Parameters
# Input Channels (ADC) | 2 |
Conversion Speed (Msps) (ADC) | 22 |
SNR (dB) (@ fIN) | 48.6 @ 5.5MHz |
Resolution (bits) (DAC) | 10 |
Output Chan. (DAC) | 2 |
Speed (Msps) (DAC) | 22 |
SFDR (dBc) (@ fOUT) | 71.7 @ 2.2MHz |
THD (dBc) (@ fOUT) | -70 @ 2.2MHz |
Noise Spectral Density (dBFS/Hz) (@ fOUT) | -128.4 @ 2.2MHz |
VSUPPLY (V) | 1.8 2.7 to 3.3 |
Package/Pins | TQFN/48 |
Budgetary Price (See Notes) | 6.92 |
Key Features
- Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs
- Ultra-Low Power
- 42mW at fCLK = 22MHz (Transceiver Mode)
- 34mW at fCLK = 15.36MHz (Transceiver Mode)
- Low-Current Idle and Shutdown Modes
- Excellent Dynamic Performance
- 48.5dB SINAD at fIN = 5.5MHz (ADC)
- 71.7dB SFDR at fOUT = 2.2MHz (DAC)
- Excellent Gain/Phase Match
- ±0.1° Phase, ±0.03dB Gain at fIN = 5.5MHz (ADC)
- Internal/External Reference Option
- +1.8V to +3.3V Digital Output Level (TTL/CMOS Compatible)
- Multiplexed Parallel Digital Input/Output for ADCs/DACs
- Miniature 48-Pin Thin QFN Package (7mm x 7mm)
- Evaluation Kit Available (Order MAX5865EVKIT)
Applications/Uses
- 3G Wireless Terminals
- Fixed/Mobile Broadband Wireless Modems
- Narrowband/Wideband CDMA Handsets
- PDAs
Description
The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 42mW at fCLK = 22Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5864 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5864 operates on a +2.7V to +3.3V analog power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 5.6mA in idle mode and 1µA in shutdown mode. The MAX5864 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin thin QFN package. See a parametric table of the complete family of pin-compatible AFEs.
Technical Docs
Data Sheet | Ultra-Low-Power, High-Dynamic-Performance, 22Msps Analog Front End | Nov 11, 2003 |
Support & Training
Search our knowledge base for answers to your technical questions.
Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .
Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.