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Analog Front-End ICs
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MAX5863
Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End
MyMaxim SubscriptionsProduct Details
Key Features
Applications/Uses
Parametric specs for Fast CODECs / Analog Front-End (AFE)
| # Input Channels (ADC) | 2 |
| Conversion Speed (Msps) (ADC) | 7.5 |
| SNR (dB) (@ fIN) | 48.6 @ 1.875MHz |
| Resolution (bits) (DAC) | 10 |
| Output Chan. (DAC) | 2 |
| Speed (Msps) (DAC) | 7.5 |
| SFDR (dBc) (@ fOUT) | 73 @ 620kHz |
| THD (dBc) (@ fOUT) | -71 @ 620kHz |
| Noise Spectral Density (dBFS/Hz) (@ fOUT) | -127 @ 620kHz |
| VSUPPLY (V) | 1.8 2.7 to 3.3 |
| Package/Pins | TQFN/48 |
| Budgetary Price (See Notes) | 0 |
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Simplified Block Diagram
Technical Docs
| Data Sheet | Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End | Nov 11, 2003 |
Support & Training
Search our knowledge base for answers to your technical questions.
Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .
Parameters
Parametric specs for Fast CODECs / Analog Front-End (AFE)
| # Input Channels (ADC) | 2 |
| Conversion Speed (Msps) (ADC) | 7.5 |
| SNR (dB) (@ fIN) | 48.6 @ 1.875MHz |
| Resolution (bits) (DAC) | 10 |
| Output Chan. (DAC) | 2 |
| Speed (Msps) (DAC) | 7.5 |
| SFDR (dBc) (@ fOUT) | 73 @ 620kHz |
| THD (dBc) (@ fOUT) | -71 @ 620kHz |
| Noise Spectral Density (dBFS/Hz) (@ fOUT) | -127 @ 620kHz |
| VSUPPLY (V) | 1.8 2.7 to 3.3 |
| Package/Pins | TQFN/48 |
| Budgetary Price (See Notes) | 0 |
Key Features
- Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs
- Ultra-Low Power
- 22.8mW at fCLK = 7.5MHz (Transceiver Mode)
- 20.7mW at fCLK = 5.2MHz (Transceiver Mode)
- Low-Current Idle and Shutdown Modes
- Excellent Dynamic Performance
- 48.5dB SINAD at fIN = 1.875MHz (ADC)
- 73dBc SFDR at fOUT = 620kHz (DAC)
- Excellent Gain/Phase Match
- ±0.03° Phase, ±0.03dB Gain at fIN = 1.875MHz (ADC)
- Internal/External Reference Option
- +1.8V to +3.3V Digital Output Level (TTL/CMOS Compatible)
- Multiplexed Parallel Digital Input/Output for ADCs/DACs
- Miniature 48-Pin Thin QFN Package (7mm x 7mm)
- Evaluation Kit Available (Order MAX5865EVKIT)
Applications/Uses
- 3G Wireless Terminals
- Fixed/Mobile Broadband Wireless Modems
- Narrowband/Wideband CDMA Handsets
- PDAs
Description
The MAX5863 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5863 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs' analog I-Q input amplifiers are fully differential and accept 1VP-P full-scale signals. Typical I-Q channel phase matching is ±0.03° and amplitude matching is ±0.03dB. The ADCs feature 48.5dB SINAD and 69dBc spurious-free dynamic range (SFDR) at fIN = 1.875MHz and fCLK = 7.5Msps. The DACs' analog I-Q outputs are fully differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase match is ±0.15° and gain match is ±0.05dB. The DACs also feature dual 10-bit resolution with 73dBc SFDR, and 61dB SNR at fOUT = 620kHz and fCLK = 7.5MHz.
The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 22.8mW at fCLK = 7.5Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5863 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5863 operates on a +2.7V to +3.3V analog power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 3.5mA in Idle Mode™ and 1µA in shutdown mode. The MAX5863 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin thin QFN package. See a parametric table of the complete family of pin-compatible AFEs.
The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 22.8mW at fCLK = 7.5Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5863 features an internal 1.024V voltage reference that is stable over the entire operating power-supply range and temperature range. The MAX5863 operates on a +2.7V to +3.3V analog power supply and a +1.8V to +3.3V digital I/O power supply for logic compatibility. The quiescent current is 3.5mA in Idle Mode™ and 1µA in shutdown mode. The MAX5863 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin thin QFN package. See a parametric table of the complete family of pin-compatible AFEs.
Technical Docs
| Data Sheet | Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End | Nov 11, 2003 |
Support & Training
Search our knowledge base for answers to your technical questions.
Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .
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