Product Details
Key Features
Applications/Uses
Simplified Block Diagram
Technical Docs
Data Sheet | 50MHz to 122.88MHz VCXO | Sep 25, 2006 |
Support & Training
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Key Features
- 50MHz to 122.88MHz Frequency
- 3.135V to 3.465V Operation
- Low Jitter: < 0.8psRMS
- ±69ppm Absolute Pull Range (APR)
- Output Options:
- LVCMOS Output Buffer
- LVDS Complementary Output Buffer
- Minimum ±110ppm Tuning Range (+25°C)
- 14mm x 9mm x 3.06mm Plastic LGA Package
Applications/Uses
- Clock-Data Recovery in Telecom/Datacom Applications
- Data Retiming
- Reference Clock Generation in Base Stations and Wireless Applications
Description
The DS4077 is designed for use with applications requiring low phase noise and jitter. Jitter performance of better than 0.8ps RMS is achieved over the 12kHz to 20MHz range. Phase noise performance of better than -125dBc/Hz at 1kHz is achieved with this design.
Technical Docs
Data Sheet | 50MHz to 122.88MHz VCXO | Sep 25, 2006 |
Support & Training
Search our knowledge base for answers to your technical questions.
Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .