Simplified Block Diagram
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- 50MHz to 122.88MHz Frequency
- 3.135V to 3.465V Operation
- Low Jitter: < 0.8psRMS
- ±69ppm Absolute Pull Range (APR)
- Output Options:
- LVCMOS Output Buffer
- LVDS Complementary Output Buffer
- Minimum ±110ppm Tuning Range (+25°C)
- 14mm x 9mm x 3.06mm Plastic LGA Package
- Clock-Data Recovery in Telecom/Datacom Applications
- Data Retiming
- Reference Clock Generation in Base Stations and Wireless Applications
The DS4077 is designed for use with applications requiring low phase noise and jitter. Jitter performance of better than 0.8ps RMS is achieved over the 12kHz to 20MHz range. Phase noise performance of better than -125dBc/Hz at 1kHz is achieved with this design.