5-Tap Silicon Delay Line

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The MXD1005 silicon delay line offers five equally spaced taps with delays ranging from 12ns to 250ns and a nominal accuracy of ±2ns or ±3%, whichever is greater. Relative to hybrid solutions, this device offers enhanced performance and higher reliability, and reduces overall cost. Each tap can drive up to ten 74LS loads.

The MXD1005 is available in multiple versions, each offering a different combination of delay times. It comes in the space-saving 8-pin µMAX package, as well as an 8-pin SO or DIP, allowing full compatibility with the DS1005 and other delay line products.
MXD1005: Functional Diagram MXD1005: Functional Diagram Enlarge+

Key Features

  • Improved Second Source to DS1005
  • Available in Space-Saving 8-Pin µMAX Package
  • 17mA Supply Current vs. Dallas' 40mA
  • Low Cost
  • Delay Tolerance of ±2ns or ±3%, whichever is Greater
  • TTL/CMOS-Compatible Logic
  • Leading- and Trailing-Edge Accuracy
  • Custom Delays Available


  • Clock Synchronization
  • Digital Systems
Request Reliability Report for: MXD1005 
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C   Material Composition  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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