Simplified Block Diagram
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- Single-Supply Operation (2.5V to 5.5V)
- 3.2W Output Power into 4Ω at 5V
- 1.8mA Quiescent Current
- 92% Efficiency (RL = 8Ω, POUT = 900mW, VDD = 3.7V)
- 29µVRMS Output Noise (AV = 6dB)
- Low 0.013% THD+N at 1kHz
- Exceptionally High Jitter Tolerance
- Supported PDM_CLK Rates of 1.84MHz–4.32MHz and 5.28MHz–8.64MHz
- Supports Left, Right, or Left/2 + Right/2 Outputs
- Sophisticated Edge Rate Control Enables Filterless Class D Outputs
- 77dB PSRR at 217Hz
- Low RF Susceptibility Rejects TDMA Noise from GSM Radios
- Extensive Click-and-Pop Reduction Circuitry
- Robust Short-Circuit and Thermal Protection
- Available in Space-Saving Package: 1.345mm x 1.435mm WLP (0.4mm Pitch)
- Cellular Phones
- Notebook Computers
- Portable Media Players
- Ultrasonic Devices
View a video that highlights the features of the MAX98355/6.
The MAX98356 takes a stereo pulse density modulated (SPDM) input signal directly into the DAC. Data on the rising edge of PDM_CLK is considered left-channel data while data on the falling PDM_CLK edge is right channel. The IC can be configured to produce a left channel, right channel, or left/2 + right/2 output from the stereo input data. The IC also features an extremely robust digital audio interface with very high wideband jitter tolerance (12ns typ) on PDM_CLK.
Active emissions-limiting, edge-rate limiting, and overshoot control circuitry greatly reduce EMI. A filterless spread-spectrum modulation scheme eliminates the need for output filtering found in traditional Class D devices and reduces the component count of the solution.
The IC is available in a 9-pin WLP package (1.345mm x 1.435mm x 0.64mm) and is specified over the -40°C to +85°C temperature range.