Single/Dual/Quad/Octal TDM-Over-Packet Chip

Supports CESoPSN, SAToP, and TDMoIP Transport Over a Packet-Switched Network for Up to 8 E1/T1 Ports

Please check latest availability status for a specific part variant.


These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial stream to be transported transparently over IP, MPLS or Ethernet networks. Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, and TDM specifications. TDM data is transported in up to 64 individually configurable bundles. All standards-based TDM-over-packet mapping methods are supported except AAL2. Frame-based serial HDLC data flows are also supported. With built-in full-featured E1/T1 framers and LIUs. These ICs encapsulate the TDM-over-packet solution from analog E1/T1 signal to Ethernet MII while preserving options to make use of TDM streams at key intermediate points. The high level of integration available with the DS34T10x devices minimizes cost, board space, and time to market.

Key Features

  • Full-Featured IC Includes E1/T1 LIUs and Framers, TDMoP Engine, and 10/100 MAC
  • Transport of E1, T1, E3, T3 or STS-1 TDM or CBR Serial Signals Over Packet Networks
  • Full Support for These Mapping Methods: SAToP, CESoPSN, TDMoIP (AAL1), HDLC, Unstructured, Structured, Structured with CAS
  • Adaptive Clock Recovery, Common Clock, External Clock and Loopback Timing Modes
  • On-Chip TDM Clock Recovery Machines, One Per Port, Independently Configurable
  • Clock Recovery Algorithm Handles Network PDV, Packet Loss, Constant Delay Changes, Frequency Changes and Other Impairments
  • 64 Independent Bundles/Connections
  • Multiprotocol Encapsulation Supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
  • VLAN Support According to 802.1p and 802.1Q
  • 10/100 Ethernet MAC Supports MII/RMII/SSMII
  • Selectable 32-Bit, 16-Bit or SPI Processor Bus
  • Operates from Only Two Clock Signals, One for Clock Recovery and One for Packet Processing
  • Glueless SDRAM Buffer Management
  • Low-Power 1.8V Core, 3.3V I/O


  • TDM Circuit Extension Over PSN
  • Leased-Line Services Over PSN
  • TDM Over G/E-PON
  • TDM Over Cable
  • TDM Over WiMAX
  • Cellular Backhaul Over PSN
  • Multiservice Over Unified PSN
  • HDLC-Based Traffic Transport Over PSN
Product Reliability Reports: DS34T101.pdf 
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C   Material Composition  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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