DS1007

7-in-1 Silicon Delay Line


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Description

The DS1007 7-in-1 Silicon Delay Line reproduces an input logic state at the output after delays at 7 taps. Delays from range from 3ns to 40ns (see table), with a tolerance of ±2ns at room temperature.

By enabling precise timing adjustments, Dallas Silicon Delay Lines improve system performance. They provide an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. Each delay line die is laser-optimized and molded into a space-saving SOIC package.

Key Features

  • All-silicon timed delay circuit
  • 7 independent, buffered delays
  • Delay tolerance ±2ns
  • Custom settings:
    • Four delays can be set between 3ns and 10ns
    • Three delays can be set between 9ns and 40ns
  • Low-power CMOS with TTL compatibility
  • Vapor phase, IR, and wave-solderable

Quality and Environmental Data

Product Reliability Reports: DS1007.pdf 
Lead-Free Package Tin (Sn) Whisker Reports
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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