Keywords: Thermal, Theta-ja, Theta-jc, heat, Theta-jb, Psi-jb
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TUTORIALS 4083

Abstract: Thermal characterization of packages is critical for the performance and reliability of IC applications. This article describes the standard thermal package properties: thermal resistance (known as \"theta\" or Θ), Θ

The thermal resistance of an IC package is the measure of the package's ability to transfer heat generated by the IC (die) to the circuit board or the ambient. Given the temperatures at two points, the amount of heat flow from one point to the other is completely determined by the thermal resistance. By knowing the thermal resistance of a package, one can calculate the IC's junction temperature for a given power dissipation and its reference temperature.

The Maxim website (Manufacturing, Layout, Production, QA/Reliability, Procurement) provides information about commonly used thermal-resistance values for ICs.

For leaded packages, the Θ

Note that Θ

Given the above definitions, we see that:

To measure Θ

Designers can determine Θ

- Control the power dissipation conditions appropriate for Θ
_{JB}or Ψ_{JB}. - Determine the die temperature, typically using a diode on chip.
- Determine the PCB temperature at < 1mm from the package's edge.
- Determine the power dissipation.

Where:

T_{J} | = junction temperature |

T_{A} | = ambient temperature, and |

P | = power dissipation in Watts |

T

Where:

T

Where:

T

Maxim listings of maximum allowable power assume an ambient temperature of +70°C and a maximum allowable junction temperature of +150°C.

Where:

T

And:

T

To find the maximum allowable power when the ambient temperature is above +70°C (for example, +85°C in the extended temperature range), proceed as follows:

JEDEC specifications are available at: JEDEC. Note that the JEDEC standards cover different thermal applications.

The thermal test board described in the JESD51-7 specification is most appropriate for Maxim IC applications.

- Front and backside: 2oz copper (0.070mm finished thickness)
- Two internal planes: 1oz. copper (0.035mm finished thickness)

Power and ground planes must be unbroken except for via isolation clearance patterns. The planes must not be present within 9.5mm of the edge connector pattern.

Electrical design tools such as PSPICE or Cadence® toolscan be used to make simple thermal models of packages. The package elements are represented as resistors connecting to the board in a resistor network. When the package model is confirmed to agree with empirical data, then the model can be used to predict package variations, including: die sizes, exposed pad sizes, fused leads, or the number of grounds connected to planes. These "what if" models give a reasonably accurate prediction of customized configurations.

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APP 4083: TUTORIALS 4083,AN4083, AN 4083, APP4083, Appnote4083, Appnote 4083 |