APPLICATION NOTE 7446

The MAX11410 Electromagnetic Compatibility

By: Tom Au-Yeung

Abstract:

The MAX11410 ADC is ideal for measuring a wide range of temperatures from -200°C to +1250°C. With proper external protection circuits, it passes all the stringent immunity standards like IEC 61000-2, 4, and 5, and high voltage 24V at the analog input tests.


Introduction

The MAX11410 is a low-power, 10-channel, 24-bit Σ-Δ Analog-to-Digital Converter (ADC) with features and specifications optimized for precision temperature sensor measurements such as Resistance Temperature Detectors (RTD) and Thermocouples. The device includes a low-noise Programmable Gain Amplifier (PGA) with very high input impedance and available gains from 1x to 128x to optimize the overall dynamic range. The programmable matched current sources provide excitation for RTD sensors. Additional current sink and current source aid in detecting broken sensor wires. The 10-channel input multiplexer provides the flexibility needed for complex, multisensor measurements. General Purpose Inputs/Outputs (GPIO) provide ease of control of external switches or other circuitries. Additionally, the MAX11410 has internal 50Hz and 60Hz filters to provide improved common-mode rejection. The MAX11410 also has self and system calibration options to reduce further software effort.

The MAX11410EMCEVKIT# is a test platform for rapid prototyping and Electromagnetic Compatibility (EMC) evaluation of the MAX11410. The MAX11410EMCEVKIT# includes an Arduino-compatible microcontroller system that performs standalone data logging. The MAX11410EMCEVKIT# also comes with schematics, design files, and firmware already loaded (source code is provided). The MAX11410EMCEVKIT# firmware can be customized and loaded using the standard Arduino tools.

The MAX11410EMCEVKIT# is built and tested to meet the transient immunity standards such as IEC 61000-2, 4, and 5. In addition, the MAX11410EMCEVKIT# is tested to ensure the device can withstand the high 24V voltage commonly used in industrial applications, which could be inadvertently applied at the analog inputs ANI0 to AIN9.

This application note discusses the methods to implement the circuitry to meet the stringent immunity standards IEC 61000-2, 4, and 5, and how to evaluate them as well as the performance data.

MAX1410EMCEVKIT# Board

Hardware Specification

The MAX11410EMCEVKIT# is fully assembled, tested, and already loaded with the DataLogger firmware. The board is powered by the USB connection to a computer. The firmware also uses the same USB serial port to communicate with the MAX11410. The data logging firmware automatically configures the MAX11410 and captures data, reporting in a format that can be saved directly to a CSV (comma-spaced-value) table format. For detailed information, refer to the MAX11410EMCEVKIT# data sheet.

Figure 1 shows the simplified schematic of the MAX11410EMCEVKIT# depicting the protection circuits at the analog inputs.

Simplified schematic of the protection circuit at analog inputsHi-res Image ›
Figure 1. Simplified schematic of the protection circuit at analog inputs.

Transient Immunity Testing

The MAX11410EMCEVKIT# was tested in Maxim Integrated's laboratory for common industrial transient immunity standards. The test methodology and results are presented in the following sections.

Performance Criteria for Immunity Tests

The results of immunity test are typically classified into four categories (Table 1). The end-application requirements and its ability to tolerate transient noise determine if the system classifies the performance criteria as a pass.

Table 1. Performance Criteria for Immunity Test

Criteria Description
Performance Criteria A Normal operation with no performance degradation.
Performance Criteria B Temporary performance degradation that is self- recoverable (data loss, data error).
Performance Criteria C Temporary performance degradation that requires intervention (device reset or power cycle).
Performance Criteria D Loss of function that is not recoverable (device damage).

IC and Board-Level Protection

The MAX11410 is designed to survive transient immunity events using a combination of integrated functionality and external (board- level) components. The MAX11410 is designed to support robust Electrostatic Discharge (ESD) performance with ±35kV ESD (HBM) specification. However, for higher energy ESD and surge pulses, such as described in IEC 61000-4-2, IEC 61000-4-4, and IEC 61000- 4-5, external transient voltage suppression (TVS) SMAJ33CA diodes are designed in the MAX11410EMCEVKIT# board to meet ESD, Electrical Fast Transients (EFT), and surge transient immunity. These diodes have extremely fast response times to respond to the 1ns rise time of the ESD pulse and excellent power dissipation capability to withstand tens of amperes of surge current. The TVS diode clamps the incoming transients to a safe level to avoid damage to the semiconductor device.

To protect the device further from being exposed to 24V high voltage at the analog inputs, BZX84C3V0W Zener diodes are used to clamp the 24V to approximately 3V, which is within the specification limit of the MAX11410 at the analog ports.

Refer to the MAX11410EMCEVKIT# for further information on the implementation of external circuitries for protection at analog inputs.

IEC 61000-4-2 Electrostatic Discharge

ESD results from electrical charge buildup and different generators for this charge are found in industrial applications. This standard covers surges with a duration of tens of nanoseconds and is more stressful than other, lower energy ESD standards such as Human Body Model (HBM) or Machine Model (MM), both of which are tested as standard for all Maxim Integrated® products and listed in the individual IC data sheets.

Contact Discharge Method: The charged electrode of the test generator is held in contact with the Device Under Test (DUT), and the discharge is actuated by the discharge switch within the generator.

Air-Gap Discharge Method: The charged electrode of the generator is brought close to the DUT, and the discharge is actuated by a spark to the DUT.

An ESD test generator is used with a 'sharp point' to make direct connection to the DUT (pin) for Contact ESD testing. A 'round tip' is added to the generator for Air-Gap ESD testing. Table 2 lists the ESD test conditions.

Output Voltage ±6kV
Polarity of the Output Voltage Positive and negative
Holding Time At least 5 seconds
Number of Applications Ten (10) consecutive ESD discharges for each polarity

Figure 2 and Figure 3 depict the IEC 61000-4-2 model and current waveform for the Contact Discharge test, respectively.

IEC 61000-4-2 ESD model test circuitFigure 2. IEC 61000-4-2 ESD model test circuit.

IEC 61000-4-2 contact discharge test waveformFigure 3. IEC 61000-4-2 contact discharge test waveform.

IEC 61000-4-4 EFT/Burst

EFTs are commonly found in industrial applications and occur from the arcing of contacts in switches and relays, as well as when large inductive loads (such as motors) are connected and disconnected.

An EFT/surge generator with an output voltage range of up to ±2kV with a 50Ω load is used to generate the voltage waveforms defined by the IEC specification. A capacitive coupling clamp provides the ability to couple the fast transients (bursts) from the EFT generator to the input, output, or power pins of the DUT without any galvanic connection to the DUT. Table 3 lists the EFT test conditions. Figure 4 and Figure 5 show the IEC 61000-4-4 EFT/Burst test setup and the waveform, respectively.

Table 3. EFT Test Conditions

Test Voltage Up to ±2kV
Polarity of the Output Voltage Positive and negative
Repetition Frequency 5kHz
Burst Duration/Repetition Time 15ms/300ms
Test Duration 60s

EFT/Burst waveform test setupFigure 4. EFT/Burst waveform test setup.

IEC 61000-4-4 EFT/Burst waveformFigure 5. IEC 61000-4-4 EFT/Burst waveform.

IEC 61000-4-5 Surge

Severe transients or surges occur during events such as lightning strikes, switching of power systems and loads, or during short-circuit fault conditions. This IEC standard specifies six classes of test levels, which depend on the end-equipment installation conditions. The class determines the protection with corresponding voltage levels. In addition, this defines the coupling mode (line-to-line or line-to- ground) and the source impedance (Zs) required. The class that most closely fits the applications using products such as the MAX11410 is Class 3 for asymmetrical operated circuits/lines with suggested test levels of ±2kV for line-to-line. Refer to the IEC 61000-4-5 standard for further details.

Table 4 lists the IEC 61000-4-5 surge test conditions. Figure 6 and Figure 7 show the IEC 61000-4-5 surge test setup and waveform, respectively

Test Voltage Up to ±2kV
Polarity of the Output Voltage Positive and negative
Waveform Parameters Front time: 1.2µs
Time to half-value: 50µs
Signal Applied Port-to-port
Port-to-ground
Repetition Rate Ten (10) surges, 10s interval for both polarities

IEC 61000-4-5 surge test setup.Figure 6. IEC 61000-4-5 surge test setup.

IEC 61000-4-5 1.2/50µs surge voltage waveformFigure 7. IEC 61000-4-5 1.2/50µs surge voltage waveform.

Surge testing is performed in accordance with the IEC 61000-4-5 specification. The 1.2/50µs combination wave generator is used for testing the MAX11410 analog inputs. Ten surge pulses of both positive and negative polarities are applied for each test condition. The pulses are applied with a 10s interval (0.1Hz). After each surge test, the MAX11410EMCEVKIT software reads the value of the device (through the Serial Peripheral Interface (SPI)) to see if the surge transient caused any damage and how much the value deviated.

The equipment used for testing the MAX11410EMCEVKIT# is listed in Table 5. Figure 8 shows the photo of the ESD gun, NSG 438, used for the ESD test, and Figure 9 shows the picture of the test bench setup for EFT/Burst and surge evaluation.

Table 5. Equipment Used for the Transient Immunity Tests of the MAX11410EMCEVKIT#

Equipment Description Test(S)
MAX11410EMCEVKIT# Device Under Test (DUT) All
ESD Test Generator Teseq® NSG 438 with Air-Gap Discharge Tip 403-826 Contact ESD and Air-Gap ESD
EFT/Surge Generator Haefely® Technology ECOMPACT4 and Teseq NSG 3040A EFT/Burst and Surge
Signal and Data Line Coupling Network Teseq CDN 117 Surge
Coupler with 0.5µF Capacitor INA 174A Surge
Capacitive Coupling Clamp Teseq CDN 3425 EFT

NSG 438 ESD gunFigure 8. NSG 438 ESD gun.

MAX11410EMCEVKIT# transient immunity EFT/Burst and surge test setupFigure 9. MAX11410EMCEVKIT# transient immunity EFT/Burst and surge test setup.

Transient Immunity Test Results

Table 6 to Table 10 include the details of specific test conditions and results for each test. For single-ended test, 1.25V is applied at AIN7. For differential test, 1.25V is applied at AIN8 to AIN9. For current test, the internal 300µA current is sourced to AIN0. AIN0 is connected to AIN2, which is connected to AIN3 through a 1KΩ resistor. Another 1KΩ resistor is connected to ground. The voltage between AIN2 and AIN3 is recorded, and the current is calculated accordingly. Figure 10 describes the test configuration.

MAX11410EMCEVKIT test configurationFigure 10. MAX11410EMCEVKIT test configuration.

Table 6. ESD Test Conditions and Results (Before and After Zap)

Input Mode Zapped Test Location(S) Test Level (KV) Before Zap (V) (Average) After Zap (V) (Average) Deviation (ppm) Results Criterion*
Single- Ended AIN7 +/-6 1.250902228 1.25089522 5.6 Pass B
Differential AIN8-AIN9 +/-6 1.250911674 1.250912413 -0.6 Pass B
Current AIN0 +/-6 0.303985703 0.303980655 16.6 Pass B

*B: Temporary loss of function or degradation of performance, which ceases after the disturbance is removed. The equipment under test recovers its normal performance without operator intervention.

ESD test. 1.25V single-ended voltage at AIN7 vs. # of samplesFigure 11. ESD test. 1.25V single-ended voltage at AIN7 vs. # of samples.

ESD test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samplesFigure 12. ESD test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samples.

ESD test. 300µA source current at AIN0 vs. # of samplesFigure 13. ESD test. 300µA source current at AIN0 vs. # of samples.

Table 7. ESD Test Conditions and Results (During Zap)

 
Input Mode Zapped Test Location Test Level (KV) Before Zap (V) (Average) During Zap (V) Deviation (ppm)
MINMAX MINMAX
Single- Ended AIN7 +/-6 1.250902228 1.25085026 1.2510466 41.54 -115.44
Differential AIN8-AIN9 +/-6 1.250911674 1.25091880 1.2506827 -5.70 183.02
Current AIN0 +/-6 0.303985703 0.30321210 0.3084540 0.25% -1.45%

B: Temporary loss of function or degradation of performance, which ceases after the disturbance is removed. The equipment under test recovers its normal performance without operator intervention.

ESD test. Before and during zap. 1.25V single-ended voltage at AIN7 vs. # of samplesFigure 14. ESD test. Before and during zap. 1.25V single-ended voltage at AIN7 vs. # of samples.

ESD test. Before and during zap. 1.25V differential voltage at AIN8 to AIN9 vs. # of samplesFigure 15. ESD test. Before and during zap. 1.25V differential voltage at AIN8 to AIN9 vs. # of samples.

ESD test. Before and during zap. 300µA source current at AIN0 vs. # of samplesFigure 16. ESD test. Before and during zap. 300µA source current at AIN0 vs. # of samples.

Table 8. EFT/Burst Test Conditions and Results
IEC 61000-4-4 Test Levels and Results of +/-2kV EFT/Burst

Input Mode Zapped Test Location Test Level (KV) Before Zap (V) (Average) After Zap (V) (Average) Deviation
(ppm)
Results Criterion *
Differential AIN8-9 -2 1.250911674 1.250912048 -0.29966731 Pass B
Current AIN0 2 0.303974231 0.303966408 25.73609482 Pass B
Current AIN0 -2 0.303985703 0.303980655 16.60480341 Pass B

B: Temporary loss of function or degradation of performance, which ceases after the disturbance is removed.

The equipment under test recovers its normal performance without operator intervention.

EFT = +2KV test. 1.25V single-ended voltage at AIN7 vs. # of samplesFigure 17. EFT = +2KV test. 1.25V single-ended voltage at AIN7 vs. # of samples.

EFT=+2KV test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samplesFigure 18. EFT=+2KV test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samples.

EFT = +2KV test. 300µA source current at AIN0 vs. # of samplesFigure 19. EFT = +2KV test. 300µA source current at AIN0 vs. # of samples.

EFT = -2KV test. 1.25V single-ended voltage at AIN7 vs. # of samplesFigure 20. EFT = -2KV test. 1.25V single-ended voltage at AIN7 vs. # of samples.

EFT = -2KV test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samplesFigure 21. EFT = -2KV test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samples.

EFT = -2KV test. 300µA source current at AIN0 vs. # of samplesFigure 22. EFT = -2KV test. 300µA source current at AIN0 vs. # of samples.

Table 9. Surge Test Conditions and Results
IEC 61000-4-5 Test Levels and Results of +/-2kV

Input Mode Zapped Test Location(S) Test Level (KV) Before Zap (V) (Average) Aafter Zap (V) (Average) Deviation (ppm) Results Criterion *
Single- Ended AIN7 2 1.250908379 1.250903119 4.204892513 Pass B
Single- Ended AIN7 -2 1.250902228 1.250896876 4.278667269 Pass B
Differential AIN8-9 2 1.250911984 1.250909759 1.77892522 Pass B
Differential AIN8-9 -2 1.250911674 1.250912421 - 0.597531498 Pass B
Current AIN0 2 0.303974231 0.303975706 - 4.852565572 Pass B
Current AIN0 -2 0.303985703 0.303982496 10.55015604 Pass B

Surge = +2KV test. 1.25V single-ended voltage at AIN7 vs. # of samplesFigure 23. Surge = +2KV test. 1.25V single-ended voltage at AIN7 vs. # of samples.

Surge = +2KV test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samplesFigure 24. Surge = +2KV test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samples.

Surge = +2KV test. 300µA source current at AIN0 vs. # of samplesFigure 25. Surge = +2KV test. 300µA source current at AIN0 vs. # of samples.

Surge = -2KV test. 1.25V single-ended voltage at AIN7 vs. # of samplesFigure 26. Surge = -2KV test. 1.25V single-ended voltage at AIN7 vs. # of samples.

Surge = -2KV test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samplesFigure 27. Surge = -2KV test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samples.

Surge = -2KV test. 300µA source current at AIN0 vs. # of samplesFigure 28. Surge = -2KV test. 300µA source current at AIN0 vs. # of samples.

Table 10. 24V Test Conditions and Results

Input Mode Zapped Test Location(s) Test Level (V) Before Zap (V) (Average) After Zap (V) (Average) Deviation (ppm) Results Criterion *
Single-Ended AIN7 24 1.250896278 1.250894903 1.1 Pass B
Differential AIN8-AIN9 24 1.250912231 1.250912502 -0.2 Pass B
Current AIN0 24 0.303983713 0.303970771 42.6 Pass B

B: Temporary loss of function or degradation of performance, which ceases after the disturbance is removed.

The equipment under test recovers its normal performance without operator intervention.

24V test. 1.25V single-ended voltage at AIN7 vs. # of samplesFigure 29. 24V test. 1.25V single-ended voltage at AIN7 vs. # of samples.

24V test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samplesFigure 30. 24V test. 1.25V differential voltage at AIN8 to AIN9 vs. # of samples.

24V test. 300µA source current at AIN0 vs. # of samplesFigure 31. 24V test. 300µA source current at AIN0 vs. # of samples.

Conclusion

The MAX11410 is a low-power, 10-channel, 24-bit delta-sigma ADC with inputs configurable for single-ended voltage, differential voltage , and internal current source to provide excitation current to the external sensors. All the three configurations were evaluated using the MAX1140EMCEVKIT# board and passed all the stringent immunity standards IEC 61000-2, 4, and 5 tests based on the laboratory characterization data. In addition, the MAX11410EMCEVIT# also passes the high voltage 24V at analog input without any damage.

References

MAX11410EMCEVKIT# data sheet

Trademarks

  • Haefely is a registered trademark of Haefely Test.
  • Teseq is a registered trademark of Teseq Holding.
  • Arduino is a registered trademark of Arduino, LLC.