How to Transmit/Receive SSMs in the DS26521 and DS2155
Apart from BITS elements like in the DS26504, DS26503, etc., normal SCTs like the DS26521 and DS2155 can also be used to transmit/receive SSMs. SSMs (synchronization status messages) defined in ANSI (T1.105) and ITU-T (G.703) recommendations identify the quality level of the incoming clock. In T1 mode, these messages are transmitted as bit-oriented codes in the datalink bits; in E1 mode, these are transmitted using one of the five Sa bits. The HDLC controllers present in the device can also be used to transmit or receive an SSM. In addition to the DS2155 and DS26521, this application note can be used to configure SSMs in the DS26514, DS26518, and DS26522 by mapping the registers.
In T1 mode, an SSM is transmitted and received in the DS26521 and DS2155 using two methods:
- BOC generator on the transmit side and a BOC detector on the receive side
- HDLC controllers
Even though HDLC controllers could be used for this purpose, using the BOC engine is recommended.
In E1 mode, an SSM is transmitted and received using the five Sa bits. An SSM is valid only when seven out of 10 messages are alike.
|BOC||Bit Oriented Code|
|CRC||Cyclic Redundancy Check|
|FDL||Facilities Data Link|
|HDLC||High-Level Data Link Control|
|SSM||Synchronization Status Message|
Procedure for Configuring the DS2155 to Transmit/Receive SSM in T1 Mode
Steps to Transmit a BOC Message
- Bits 0 to 5 of the TFDL register must be loaded with messages to be transmitted. The message is transmitted as 0xxxxxx0 11111111, where x’s represent an actual SSM. The transmit BOC controller automatically handles the 0s and ignores FFh. The respective FDL code from Table 1 should be loaded to the TFDL register from bit 0 to bit 5.
|Quality Level||Description||FDL Code Word (DS1 ESF)|
|1||Stratum 1 traceable||0 0000100 11111111|
|2||Synchronized traceability unknown||0 0000100 11111111|
|3||Stratum 2 traceable||0 000110 0 11111111|
|4||Stratum 3 traceable||0 0000100 11111111|
|5||SONET minimum clock traceable||0 0100010 11111111|
|6||Stratum 4 traceable||0 010100 0 11111111|
|7||Do not use for synchronization||0 011000 0 11111111|
|User Assignable||Reserved for network synchronization use||0 100000 0 11111111|
- Set bit 0 of the BOCC register to 1 to start transmitting the SSM.
Figure 1. BOCC control register description.
- Set bit 0 of the receive BOCC register to 1.
- Enable the receive BOC change of state interrupt by bit 0 of the IMR8 register to 1.
- Bit 0 of the SR8 register indicates if any change of state interrupt has occurred.
- The lower 6 bits of the RFDL register contain the received BOC messages.
The host can then read the RFDL register for the received BOC message. Bit 7 of the SR2 register is set if the received BOC message is valid.
Procedure for Configuring DS2155 to Transmit/Receive SSM in E1 ModeSteps to Transmit SSM
On the transmit side, Sa bits can be inserted into the Sa bit control registers (TSACR).
- Load any register among TSa4 to TSa8 with the SSM code to be transmitted.
- Set bit 4 of SR4 register to start transmitting the SSM.
Figure 2. SR4 register description.
- TASCR, which is the transmit Sa-bit control register, should be configured to insert data from the TSa4:TSa8 register into the transmit data stream.
- Set bit 1 of SR4 register. This enables CRC4 multiframe boundaries.
- The received Sa bits are stored in RSa4 to RSa8. Any of these registers can be selected to receive the incoming Sa bits.
Procedure for Configuring DS26521 to Transmit/Receive SSM in T1 ModeSteps to Transmit SSM
- Write 6-bit SSM code into T1TBOC register.
- Set bit 6 (SBOC) of THC2 register to enable SSM transmission.
Figure 3. THC2 register description.
- Bit 0 of the RLS7 register is set when a valid BOC message is received.
- T1RBOC register contains the received BOC message.
Procedure for Configuring DS26521 to Transmit/Receive SSM in E1 ModeSteps to Transmit SSM
- E1TSa4:E1TSa8 registers can be used to send SSM.
Figure 4. E1TSa4 register description.
Note: The lower nibble and higher nibble of this register should be loaded with the same SSM code.Table 2. SSM Codes for E1 Operation
|Quality Level||Description||San1, San2, San3, San4
(where n = bit number 4, 5, 6, 7, or 8)
- E1TASCR, which is the transmit Sa-bit control register, should be configured to insert data from the TSa4:TSa8 register into the transmit data stream.
Figure 5. E1TSa4 register description.
- CRC-4 multiframe mode should be enabled in the E1TCR1 register.
Figure 6. TCR1register description.
- Wait for Bit 1 of RLS2 register to set.
- The received SSM code is in any of the RSa4:RSa8 registers.