Paralleling Ideal Diodes: Using the MAX40200 as a Scalable Building Block
The MAX40200 is an ideal diode current switch that drops so little voltage that it approaches an order of magnitude better than Schottky diodes. The device thermally protects itself, and any downstream circuitry, from overtemperature conditions. When disabled (EN = low), it blocks voltages up to 6V in either direction, making it suitable for most low-voltage, portable electronic devices. When reversed-biased, it leaks less than many comparable Schottky diodes. The MAX40200 operates from a 1.5V to 5.5V supply voltage.
The MAX40200 ideal diode has many benefits including the following:
- Low 7μA quiescent supply current
- Low power dissipation at 1A, just 125μW
- Tiny voltage-drop of approximately 18mV for IF up to 100mA
- Less than 100μs reverse/turn-off times
- 4-bump WLP space-saving package
- Enable/disable control and thermal shutdown
In many circuits, the functionality of an ideal diode is required but at much higher currents. One useful aspect of ideal diodes such as the MAX40200 is that because they are implemented with MOSFETs and not diodes, they inherently share any load current. This application note investigates using multiple MAX40200 devices in parallel and their combined performance.
The multiple ideal-diode solution should provide the same characteristics of a single, larger device with a factor based on the number of MAX40200 devices being used. This allows us to use two in parallel for a 2A system and, by extension, four in parallel for a 4A system.
Figure 1 shows four MAX40200 devices paralleled to up to 4A of current. If the devices are placed closer to each other, the temperature of each device is close to one another. Since the devices are at same temperature, they are expected to have similar characteristics. Figure 1a shows the DC characteristics of forward drop vs. forward current. Figure 1b shows a comparison of one MAX40200 device and four MAX40200 devices, confirming that the characteristics of one MAX40200 device and four MAX40200 devices are very similar.
Figure 1. Typical application circuit to increase current sharing to carry high currents.
Figure 1a. Curves a, b, and c are DC characteristics showing the forward drop across the devices vs. forward current through them.
Figure 1b. Comparison of one MAX40200 device and four MAX40200 devices.
Figure 2 shows the schematic setup for enable and disable response of the application circuit. Curves 2a and 2b shows the observed results.
Figure 2. Setup for enable/disable response.
Curve 2a. Enable transient (IFWD = 4A).
Note that the VIN exhibits a significant transient in the above figure. This is due to the load regulation response of the power supply used when sourcing from 0 to 4A. This transient effect is also seen at the VLOAD.
Curve 2b. Enable/disable transient (IFWD = 4A).
Curve 3a shows the load transient response. Figure 3 shows the schematic circuit setup to measure load transient response. There could be certain scenarios where heavy loading can occur for a short burst of time and the pass device must be able to provide such amounts of currents with little to no variation on the VFWD (V). This is because VLOAD (V) is usually the power supply for subsequent circuits.
Figure 3. Setup for load transient response.
Curve 3a. Load transient response (IFWD = 200mA to 3.8A).
The below setup schematic shown in Figure 4 uses a standard Schottky diode (CMSH5-20: 20V, 5A Schottky) in conjunction with four MAX40200 devices. A transient is created at VIN2 to simulate a diode ORing/power-path-select scenario.
When VIN2 (3.3V) is less than VIN1 (3.6V), VIN1 is selected and diode D1 is reverse-biased. When VIN2 is greater than 3.6V, D1 starts conducting and U1 to U4 turns off. Curve 4a shows the transient response of the Figure 4 circuit.
Figure 4. Diode ORing application using a standard diode and four MAX40200 devices.
Curve 4a. Diode ORing transient response.
Curve 4b. Diode ORing transient response.
PCB Layout Considerations
Figure 5 shows a typical example of board layout using four MAX40200 paralleled devices. As shown, the VDD and OUT traces on the board have considerable island space of copper pour to decrease the trace resistance and decreasing the current density. Both the VDD and OUT traces are present on the top layer and no vias are used. Since the physical mechanism that ensures load-current sharing is thermal, the paralleled ideal diodes should be located as close as practical to each other. Given that currents are presumably quite large, or one would not need to parallel the parts, the PCB should use the thickest copper available. Doing so helps spread the heat and reduces voltage drops at high currents. Note that the WLP package is optimal for paralleling multiple units because the small size and good thermal conductivity allow sufficient thermal coupling to make this approach practical.
Figure 5. Example of layout technique.
As shown in Figure 6, the parts are placed 12mm (484 mils) apart from each other, which ensure all the MAX40200 devices are thermally equivalent. Keep the paralleled devices away from significant external heat sources. Failure to do so would have all the devices operating at higher temperatures, thereby increasing the internal RON. Unequal board temperature on each of the devices results in unequal current sharing. Vias on the main path (VDD or OUT) are not recommended as they add parasitic inductances and increase the effective RON on the forward path, thereby increasing the voltage drop (VFWD).
Figure 6. Distance between adjacently placed MAX40200 device.
Figure 7 shows the temperature difference between the ambient and the board containing paralleled MAX40200 devices. You can observe that the temperature difference is directly proportional to the forward load current passed through the devices. This result was obtained using the board from Figure 5.
Figure 7. Regulated ambient board temperature vs. ambient temperature.
Why Using Multiple Parallel Devices Works So Well
The MOSFET's on-resistance has a strong, positive temperature coefficient, which ensures that the hotter MOSFET has more resistance than the cooler MOSFET, forcing the cooler MOSFET to take a little more current. The two MOSFETs, therefore, establish a thermal equilibrium matching the current balance. Good PCB layout ensures this thermal equilibrium. In general, placing the parts close together is sufficient, but if there is another device on the PCB that dissipates a lot of heat, the thermal gradient set up by such a device alters the current-sharing balance of the paralleled ideal diodes.
Wafer Level Package and Packaged Device Differences
The above investigation was carried out for the WLP (wafer level package) and is optimal for paralleling multiple units because the very small size, its package characteristics, and good thermal conductivity allow sufficient thermal coupling to make this approach practical.
Due to the higher thermal resistance of the SOT23 package (internal bond wire resistance), the current sharing the forward-voltage drop (VFWD) is not as good as with the WLP counterpart. Also, any additional thermal gradients have a significant effect even when the SOT packages are very closely spaced. It is recommended to derate the ideal diodes in this package to 75% of full specification.
The MAX40200 has been shown to scale well when connecting two in parallel as well as four in parallel. Both DC characteristics and transient responses show that current sharing is close to ideal and the transient performance is not degraded. The MAX40200 is scalable, allowing it to be used in many applications requiring higher currents, or for lower voltage drops than a single part could handle.