Keywords: Leaded packages, SMT, PCB design, SOIC, TSSOP, QSOP, SC70, SOT, SOP, QFP
Leaded packages are surface-mount integrated circuit (IC) packages, including such types as quad flat package (QFP), small outline integrated circuit (SOIC), thin shrink small-outline package (TSSOP), small outline transistor (SOT), SC70, etc. The standard form is a flat rectangular or square body, with leads extending from two or all four sides. The leads are formed in a gull wing shape to allow solid footing during assembly to a PCB. Standard Pb-free lead finish is matte tin. Connection is made through the leads of the package, which can be directly soldered onto the PCB. When an exposed pad is provided in some packages for thermal enhancement purposes, the exposed pad should be directly soldered onto the PCB. Figure 1 shows the cross-section profile of a leaded package.
Figure 1. Cross-section view of leaded package.
Package information is available on our website at www.maximintegrated.com/packages. Users can review package outline drawings specific to a package type or package code.
For PCB pad design: a well-designed and manufactured printed circuit board (PCB) is required for optimum manufacturing yields and product performance. Two types of land patterns are used for surface-mount devices: 1) solder mask-defined (SMD) pads have solder mask openings that are smaller than metal pads, and 2) nonsolder mask-defined (NSMD) pads have solder mask openings that are larger than the metal pads. Maxim recommends the use of NSMD pads because they provide a larger metal area for the solder to anchor to the edges of the metal pads. NSMD improves the solder joint reliability. Only one type of a pad (NSMD or SMD) and one type of pad surface finish should be used at a given footprint. Figure 2 illustrates the NSMD and SMD land pattern design.
Land pattern design should follow Maxim’s 90-xxxx series documents corresponding to the specific package code.
Figure 2. Illustration of NSMD and SMD land pad patterns.
Thermal pads on the PCB should be designed to take advantage of the exposed pads of the packages provided. For a single-layer board, a thermal pad should be connected to a large surface pad, so that heat can be dissipated through the surface pad. For a multiple-layer board, thermal via(s) should be placed under the thermal pad, so that heat can be dissipated to other metal layers to take advantage of metals in the those layers. The thermal via(s) design should be optimized based on PCB manufacturer capability and other design limitation.
Organic solderability preservative (OSP), electroless nickel immersion gold (ENIG), electrolytic nickel gold, electroless nickel electroless palladium immersion gold (ENEPIG), immersion silver, and immersion tin finishes are used in the industry. OSP and ENIG are recommended for applications that require drop test reliability.
The stencil thickness and pattern geometry determine the precise volume of solder paste deposited onto the device land pattern. Stencil alignment accuracy and consistent solder volume transfer is critical for uniform solder reflow. Stencils are usually made of stainless steel.
The exposed pad solder land can be segmented into a pad array. The pad array should be created by segmentation of a full copper area by solder mask webbing. The segmented PCB design facilitates the solder paste flux out gassing during reflow, thereby promoting a lower voids percentage of the completed solder joint. At the same time, the maximum size of a single solder void is limited by the dimensions of a single matrix segment. Figure 3 shows an example of a solder mask design for an exposed pad.Design Recommendation:
Figure 3. Example of solder mask design for exposed pad.
Solder paste is one of the most important materials in the SMT assembly process. In general, it is recommended to use a no-clean solder paste. However, the end user should evaluate their entire process and usage to ensure desired results. A Type 3 (or finer) solder paste is recommended for 0.5mm pitch printing. Nitrogen purge is recommended during solder reflow.
If a low residue, no-clean solder paste is used, PCB cleaning is not required. However, with different types of no-clean solder pastes available, Maxim recommends application-specific evaluations to check if any remaining residue needs to be removed from the boards.
Maxim leaded packages are compatible with all industry-standard solder reflow processes. As with all surface-mount devices, it is important that profiles be checked on all new board designs. Additionally, if there are tall components mixed on the board, the profile must be checked at different locations on the board. Component temperatures may vary due to surrounding components, locations of parts on the PCB, and package densities. The reflow profile guidelines are based on the temperature at the actual lead to PCB land pad solder-joint location. The actual temperature of the solder joint is often different than the temperature settings in the reflow system. Therefore, Maxim recommends the profiles be checked using thermocouples at the actual solder joint location. A nitrogen force convention oven should be used. Temperature uniformity should be 5°C.
Maxim suggests following the JEDEC recommended reflow profile, J-STD-020E.Table 1. Recommended Pb-Free Reflow Profile
|Profile Feature||Description||Pb-Free assembly Recommendation|
|TSmin||Min Soak Temperature||150°C|
|TSmax||Max Soak Temperature||200°C|
|TS||Time Between TSMIN and TSMAX||60–120 Seconds|
|TL||Time Above TL||60-150 seconds|
|TP||Peak Package Body Temperature||260°C|
|TP||Time Within 5°C of TP||30 Seconds|
|Ramp-Up Rate (TL to TP)||3°C/Seconds (max)|
|Ramp-Down Rate (TP to TL)||6°C/Seconds (max)|
Figure 4. Classification of reflow profile.
Maxim suggests following the IPC specification for inspection specs. Go to www.ipc.org for more information. Figure 5 shows one example of a well-soldered lead. The solder fillet should be able to be visually inspected at both sides, but not over the solder on top of the leads.
Figure 5. Well-soldered lead on a well-designed PCB.
Maxim leaded packages are classified as JEDEC standard per specification J-STD-020D.
For those packages that only meet MSL3 (typically larger packages and special packages), all parts are baked and dry-packed with desiccants and a humidity indicator card before shipping. If the humidity indicator card has turned pink, or if the parts have been exposed to longer than their floor life, bake the packages +125°C for 48 hours.
Refer to JEDEC specification J-STD-020D for correct use of moisture/reflow sensitive surface-mount devices.
The rework quality is not easily controlled. If rework is needed on the parts with soldering defects, Maxim suggests baking the PCB assembly at least 4 hours at +125°C. Use the following steps as minimum:
Conventional placement systems can be employed using either the package outline or the position of the leads as a placement guide. Placement guide using position of the leads tends to be more accurate but slower, and requires a complex vision-processing system. The package outline placement method runs faster, but is less accurate. The contract PCB assembler can determine the most acceptable method to be employed for this process.
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APPLICATION NOTE 6412,AN6412, AN 6412, APP6412, Appnote6412, Appnote 6412