Keywords: QFN, Side Wettable, SMT, PCB design
The quad flatpack, no leads (QFN) package is a leadless, near chip-scale package (CSP), plastics-encapsulated package with copper lead frame as substrate. All QFNs are leadless packages where the connection is made through the leads (terminal pins) and exposed pads on the bottom surface of the package. These leads (terminal pins) and exposed pads can be directly soldered onto the PCB. This application note discusses the guidelines necessary for proper PCB design and SMT assembly when using Maxim's QFN leadless packages.
Maxim's QFN package comes in two package singulation formats: punched QFN and sawn QFN. Figure 1a and Figure 1b show a package cross section of each format.
|Figure 1a. Punched QFN package cross-section drawing.||Figure 1b. Sawn QFN package cross-section drawing.|
Maxim also offers flip-chip QFN (FC-QFN) packages, where the die is connected to the lead frame using solder ball or Cu pillar interconnects. Figure 2 shows a sawn FC-QFN package cross section.
Figure 2. Sawn flip-chip QFN package cross section.
For select end applications, designers may want to visually inspect the solder joint formation on the QFN terminals using an automated optical inspection tool. For these select applications, designers should consider the side-wettable QFN package option.
Maxim's side-wettable QFN package options use geometrical solutions such as half-cut lead frame, half-etch lead frame, or dimpled lead frame to create an externally visible solder joint that can be inspected optically after reflow soldering. Figure 3a shows a dimpled side-wettable QFN drawing, and Figure 3b shows a half-cut side wettable QFN drawing.
|Figure 3a. Dimpled side-wettable QFN package drawing.||Figure 3b. Half-cut side-wettable QFN package drawing.|
Package Surface Mount Considerations
Special considerations are needed to properly design the PCB to mount the package. For enhanced thermal, electrical, and board level performance, the exposed pad on the package needs to be soldered to the board using a corresponding thermal pad on the board.
For proper heat conduction through the board, thermal vias need to be incorporated into the PCB in the thermal pad region. The PCB footprint design must be considered from dimensional tolerances due to package, PCB, and assembly. Many factors can have significant effects on mounting the package on the board and the quality of solder joints. Designers must consider these factors, which include the following:
This application note provides designers with the guidelines for board design considering these factors. It should be emphasized that this document is strictly a guideline to help the user in developing the proper motherboard design and surface mount process. Actual studies as well as development effort may also be needed to optimize the process as per the user's surface-mount practices and requirements.
A well-designed and manufactured printed circuit board (PCB) is required for optimum manufacturing yields and product performance.
Two types of land patterns are used for surface-mount devices:
Maxim recommends the use of NSMD pads because they provide a larger metal area for the solder to anchor to the edges of metal pads on the board for improved solder joint reliability.
Figure 4. Cross section drawing of NSMD. Note: There should not be any mixture of SMD and NSMD pads within the same QFN footprint. Maxim recommends the inclusion of fiducial marks in proximity to the QFN package to facilitate component placement.
PCB Land Pattern Dimensions
Maxim's land pattern drawings for QFN packages can be downloaded from our website at: www.maximintegrated.com/packages. IPC land pattern calculator (IPC-7351) can be downloaded from the IPC website at: www.ipc.org.
Maxim does not recommend designing vias, untented with solder mask, close to the package lead terminal and underneath the corners of the package where tie bars terminate. Refer to IPC-7351 for “Land Pattern to Via Relationship” design recommendation.
PCB Pad Pattern for Lead Terminals
As a guideline, lead finger length dimension (Y) should be designed using the following considerations:
For lead finger width dimension (X) should be designed using the following considerations:
|Figure 5a. Lead terminal length.||Figure 5b. Lead terminal width.|
PCB Pad Surface Finish
The selection of an appropriate PCB pad surface finish is critical to ensuring optimum manufacturing of the final board assembly. Table 1 compares several popular surface finishes.
|Copper OSP||Organic solderability preservative (OSP)||Acceptable||—|
|ENIG||Electroless nickel immersion gold||Acceptable||—|
|Silver Immersion||Thin layer silver electroless plated||Acceptable||Silver immersion thickness must be controlled (0.150mm to 0.625mm to minimize micro voids at the solder joint|
|Gold Immersion||Thin layer gold electroless plated||Acceptable||—|
|HASL||Hot air solder leveling||Acceptable||Process must be controlled to provide solder coverage of small mask openings|
Stencil Design Guidelines
The stencil thickness and pattern geometry determine the precise volume of solder paste deposited onto the device land pattern. Stencil alignment accuracy and consistent solder volume transfer is critical for uniform solder reflow. Stencils are usually made of stainless steel.
Figure 6. Stencil cross section.
Figure 7. Stenceil design for exposed pads.
A low-residue, no-clean solder paste is commonly used in mounting QFNs. Water-soluble flux materials are not recommended as there is minimal standoff (distance of package to PCB) and it will, therefore, be very difficult to clean flux trapped underneath the package.
A Type 3 (or finer) solder paste is recommended for 0.5mm pitch printing. Nitrogen purge is recommended during solder reflow.
Recommended lead(Pb)-free solder paste: SAC305 (Sn-Ag-Cu) alloys
An automatic or manual stencil/screen printer can be used to distribute the solder paste onto the PCB lands.
A design of experiments (DOE) should always be used to establish optimum printing parameters. Most assemblers find that the following parameter ranges serve as good starting points:
A stainless steel squeegee should be used. Multiple printing of solder paste should be avoided for fine pitch devices, as it may cause smearing of the solder paste.
Conventional placement systems can be employed using either the QFN outline or the position of the leads as a placement guide. Placement guide using position of the leads tends to be more accurate but slower, and requires a complex vision processing system. Package outline placement method runs faster but is less accurate. The contract PCB assembler can determine the most acceptable method to be employed for this process. The QFN package is expected to a good self-centering ability similar to a BGA package.
Maxim QFNs are compatible with all industry-standard solder reflow processes. It is important that profiles be checked on all new board designs. Additionally, if there are tall components mixed on the board, the profile must be checked at different locations on the board. Component temperatures may vary due to surrounding components, locations of parts on the PCB, and package densities.
The reflow profile guidelines are based on the temperature at the actual lead to PCB land pad solder-joint location. The actual temperature of the solder joint is often different than the temperature settings in the reflow system. It is recommended that reflow-specific profiles be checked using thermocouples at the actual solder-joint locations and following the paste supplier's recommendations.
Nitrogen reflow is recommended to improve solderability and to reduce defects such as solder balls. Figure 8 is one reflow example for Pb-free temperature profile per JEDEC J-STD-020.
Figure 8. JEDEC lead-free reflow profile.Table 2. Recommended Pb-free Reflow Profile
|Lead (Pb) free reflow profile feature||Description||Pb-Free assembly recommendation|
|TSmin||Min Soak Temperature||150°C|
|TSmax||Max Soak Temperature||200°C|
|tS||Time Between TSMIN and TSMAX||60–120 Seconds|
|tL||Time Above TL||60-150 seconds|
|TP||Peak Package Body Temperature||260°C|
|tP||Time Within 5°C of TP||30 Seconds|
|TL to TP||Ramp-Up Rate||3°C/Seconds (max)|
|TP to TL||Ramp-Down Rate||6°C/Seconds (max)|
|—||Time 25°C to Peak Temperature||8 Minutes (max)|
Post-reflow inspection of QFNs on PCBs is typically accomplished by using transmission-type X-ray equipment. X-ray can be used for reflow process monitoring and as a failure analysis tool. A 2D X-ray system with oblique view at highest magnification (OVHM) is recommended as it can detect solder bridges, opens, and voids.
Standard QFN packages
Standard QFN packages do not have any externally visible features that allow one to check if the package has been successfully soldered to the board. As in any leaded package technology, the edges of the leads will have exposed bare copper. Bare copper is not sufficient to ensure side wetting.
Lack of solder wetting in this area should not be considered as a criterion for visual inspection rejection. Maxim does not guarantee formation on solder fillet (toe fillet) as the sides of these lead terminals will have an exposed copper post-package singulation.
Side-Wettable QFN Packages
The specifically introduced geometric features in a side-wettable package (half-cut/half-etch/dimple) allow for a visible solder fillet to form on the side of all peripheral pins (Figure 9). The fillet can be visually inspected if the pins are soldered successfully to the PCB pads. The full height of the geometrical structure needs to be covered by solder fillet.
Figure 9. Half-cut side-wettable and dimpled side-wettable QFN.
If a low residue, no-clean solder paste is used, PCB cleaning is not required. However, with different types of no-clean solder pastes available, Maxim recommends application-specific evaluations be performed to identify if any remaining residue needs to be removed from the boards.
An appropriate rework station should be used for any rework on the parts.
Prior to any rework, it is strongly recommended that the PCB assembly be baked for at least 4 hours at 125°C to remove any residual moisture before component removal.
During the removal process, it is recommended that the board be heated from the bottom side using convective heaters, and hot gas or air should be used on the top side of the component. Special nozzles should be used to direct the heating to the component only and minimize heating of adjacent components.
Maximum part temperature should be above the liquidus temperature of 217°C, but should not exceed 260°C. Once the joints have reflowed, the vacuum lift-off should be automatically engaged during the transition from reflow to cool down. The vacuum pressure should be kept below 15in of Hg to ensure the component is not lifted out if all joints have not been reflowed.
Following component removal, the site must be cleaned properly without damaging the pads. Once the residual solder has been removed, the lands should be cleaned with a solvent. The solvent is usually specific to the type of paste used in the original assembly. Paste manufacturer’s recommendations should be followed.
Solder Paste Printing
It is recommended that a miniature stencil be used to print solder paste on the PCB surface at the component site.
Follow stencil thickness, stencil design, solder recommendations, and screen-printing guidelines, as provided for original PCB assembly. Align stencil with the pads under 50X magnification to inspect the site before replacing with a new component (part).
QFN packages have superior self-centering ability similar to BGA packages. Because the leads are on the package’s underside, a split-beam optical system should be used to align the component on the board. Doing so forms an image of the leads overlaid on the mating footprint and aids in proper alignment. A placement machine having a 0.05mm placement accuracy should be used.
The same reflow profile developed during initial component attachment should be used to attach the new component followed by the post reflow inspection step.
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|© , Maxim Integrated Products, Inc.|
APPLICATION NOTE 6382,AN6382, AN 6382, APP6382, Appnote6382, Appnote 6382