MAX2880 Application Note: Designing A 12GHz, Ultra-Low Phase Noise (0.09 ps rms jitter) Phase Locked Loop

By: Jun Liu

Abstract: This application note is a detailed design guide and characterization report of a complete 12GHz, ultra-low phase noise fractional-N phase locked loop (PLL) with external VCO and active loop filter.


This application note details the design of a complete 12GHz, ultra-low phase noise fractional-N phase locked loop (PLL) with external VCO. It consists of a high performance fractional-N PLL (MAX2880), op-amp based active loop filter (MAX9632), and 12GHz VCO (SYNERGY DXO11751220-5).

12GHz ultra-low phase noise fractional-N PLL based on MAX2880. Figure 1. 12GHz ultra-low phase noise fractional-N PLL based on MAX2880.

Key Features:

  • Ultra-Low Phase Noise: 92-Femtosecond RMS Jitter (1kHz-20MHz)
  • No External Frequency Divider Needed
  • Active Filter with Tuning Range from 0.5V to 15V

This high performance PLL can be used to generate a mixer local oscillator (LO) frequency or an ADC/DAC clock for applications in microwave point-to-point systems, test and measurement equipment, or automotive radars.

Phase noise performance data and detailed setup guide are included in this app note.

Performance results:

PLL overall phase noise is usually dominated by the PLL's inband phase-noise floor and VCO phase noise. To build an ultra-low phase-noise PLL, the designer needs to select a low-phase noise VCO and PLL. The MAX2880 is capable of achieving an inband phase noise floor of -229dBc/Hz for integer mode and -225dBc/Hz for fractional low-noise mode.

Table 1 and Figure 2 show the phase noise performance of the circuit at 12GHz and different modes of the MAX2880.

Table 1. 12GHZ Phase Noise Summary
Parameter Result Unit
Carrier Frequency 12 GHz
RMS Jitter (Integer Mode ) 89 femtosecond
RMS Jitter (Fractional Low-Noise Mode ) 92 femtosecond
RMS Jitter (Fractional Low-Spur Mode ) 140 femtosecond
SSB Integrated Phase Noise (Integer Mode ) -46.7 dBc
SSB Integrated Phase Noise  (Fractional Low Noise Mode ) -46.2 dBc
SSB Integrated Phase Noise  (Fractional Low Spur Mode ) -42.7 dBc
Integration Limit 1-20,000 kHz
VCO Tuning Range 0.5-15 V

12GHz phase noise plot. Figure 2. 12GHz phase noise plot.

Detail Setup Guide:

A MAX2880 evaluation kit (EV kit) and a 12GHz external VCO (Synergy DXO11751220-5) are required for this design.

Note: the Synergy VCO is not included in the MAX2880 EV kit, and some modifications of the EV kit are required.

  1. Verify default MAX2880 functionality. Follow the MAX2880 EV kit datasheet for detailed operating procedure.
  2. Modify the MAX2880 EV kit according to Table 2 and change the jumper positions according to Figure 3.

    Table 2. MAX2880 EV Kit Modifications

    Part (unit) Change Default Note
    C1 (nF) Open 10 Remove passive filter
    R2A (ohm) Open 100 Remove passive filter
    C2 (nF) Open 100 Remove passive filter
    R3 (ohm) Open 47.5 Remove passive filter
    C3 (nF) Open 1 Remove passive filter
    R4 (ohm) Open 0 Remove passive filter
    R27 (ohm) 0 Open Connect active filter
    R26 (ohm) 4300 Open Active filter
    C4 (pF) 15 Open Active filter
    C101 (pF) 150 Open Active filter
    R102 (ohm) 560 Open Active filter
    C102 (pF) 8200 Open Active filter
    R9 (ohm) Open 16.9 disconnect onboard VCO
    R9 to NC1 16.9 Open connect external VCO
    JP4 2 pin jumper Open Connect power down onboard VCO
    JP5 3 pin jumper connect center pin  to 5P0_VCC Open pamp input+ bias
  3. Make the connections to the EV kit according to Figure 4. Make sure all power supply units are OFF.
  4. Power up the VCO to +5V.
  5. Power up the MAX2870 EV kit with +15V and +6V.
  6. Program the MAX2880 registers for the desired mode:

    Integer Low-Noise mode: 003C0000,06000001,6F00CE22,00002503,00000004,00000005
    Fractional Low-Noise mode: 003C0000,06000001,0F00FFFA,00000303,00000004,00000005
    Fractional Low-Spur mode: 003C00C8,06000001,6F00CE22,00000B03,00000004,00000005

Jumper position. Figure 3. Jumper position.

Detail setup diagram. Figure 4. Detail setup diagram.