Extending I2C Communication Distance with the DS28E17
The maximum distance of an I2C bus depends on the capacitive loading. In typical applications, the length is limited to a few meters in standard mode. This is because a system has to be built to accommodate a maximum bus capacitance of 400pF to meet rise time requirements listed in the I2C bus specification (Rev. 6 – 4 April 2014). To achieve greater distances by operating above the maximum allowable bus capacitance, the I2C bus specification allows operating at a lower speed, using higher drive output devices, dividing the bus into segments with bus buffers, or the use of switched pullup circuits. While on the surface these methods may seem viable, they either do not meet the long-distance requirements or significantly increase the cost. An alternative is to use the DS28E17 1-Wire-to-I2C Master Bridge.
The DS28E17 1-Wire-to-I2C Master Bridge takes a different approach by utilizing the 1-Wire® protocol as shown in Figure 1. The distance can be extended because the protocol can tolerate a larger amount of bus capacitance. The use of a single-conductor twisted pair for the 1-Wire bus and ground return keeps the solution costs low.
Figure 1.Typical application circuit.
By using a few simple circuit fundamentals, the circuit in Figure 1 bus capacitance can be examined. Here are basic steps to take:
1) Determine the capacitance of each element in the system.
- CAT5E cable capacitance per meter: 52pF/m
- Near-end input capacitance (i.e., µC or DS2484): 10pF
- Far-end input capacitance (i.e., DS28E17): 15pF
2) Calculate the total 1-Wire bus capacitance in the system for your length of cable.
CBUS = (CCABLE per meter × Length) + CNear End + CFar End
CBUS = (52pF × 100m) + 10pF + 15pF
CBUS = 5.23nF
3) Determine the 1-Wire master capacitive drive capability (i.e., µC or DS2484). This needs to be determined for low-to-high transitions (i.e., the rising edge) because this is affected the most by bus capacitance. A high-to-low transition (i.e., the falling edge) is always driven by the 1-Wire master with a decent pulldown (i.e., ~8mA) and can usually be ignored.
- Set the timeslot timing limits to allow maximum rise time.
- tRL = tW1L value set in firmware: 5µs
- tMSR value set in firmware: 15µs
- µC capacitive drive capability:
- RPUP value: 680Ω
- Determine the rise time for two time constants (2τ or 86.5% of VCC). This is set by the DS28E17's standard speed read timeslot requirements for long lines and the µC's VIHmax parameter (e.g. usually in a range of VCC x 0.6 to VCC x 0.85 for most systems).
- Using first-order RC circuit approximation yields the maximum capacitive drive capability allowed for the system with the µC.
4) Verify that the 1-Wire bus capacitance does not exceed the capacitive drive capability of the 1-Wire master.
- µC check: CBUS < CBUSmax (i.e., 5.23nF < 7.35nF).
- DS2484 check: CBUS < CBUSmax (i.e., 5.23nF < 15nF).
5) Adjust the 1-Wire recovery time (tREC) for long lines in the 1-Wire master's firmware.
- µC's firmware set to: tREC..FW ≈ 2τ + tRECmin (i.e., 15µs = 2 x 5µs + 5µs).
- DS2484's firmware set to: tREC..FW ≈ τ + tRECmin (i.e., 10µs = 5µs + 5µs).
This application note provides an alternative method to extend an I2C bus. It also provides basic equations and the design philosophy to check the bus capacitance in a long line application with the DS28E17.