Maxim Integrated’s JIBEPOS Current Measurement

By: Reza Ahmadi

Abstract: This application note provides information on a typical use case of the JIBEPOS reference design power consumption under certain conditions.

This document is written for a highly specific application and contains information about proprietary technology, and is only available to customers whose requirements closely match the application. To request the full document, please complete the form below.

Please enter information in English only.


The power consumption specifications in the data sheet of a chip are not always the best representation of real-life application. This application note tries to explain the setup and typical conditions under which the measurements are taken for the JIBEPOS reference design. At the end, the results are presented in graphical form.

Setting Up

To measure the current on different supply lines (1.0V, 1.8V, and 3.3V), the on-board power supply is removed and each power-rail is fed directly by Tektronix PWS2721 DC power supplies. The current measurement is completed on the Tektronix DMM4040 6½ Digital Precision Multimeter. These multimeters have the ability to log the current over a period of time.

Test setup is shown in Figure 1.

Test setup. Figure 1. Test setup.


Let the JIBEPOS power up normally. As it goes through different sequences such as loading the u-boot to internal memory, loading the kernel to external LPDDR, and booting the kernel from there, the current consumption is logged during each operation. Besides the booting sequence, we implement two different use cases:

  1. Smart card test operation. During this test, 2500 challenge APDU transactions are performed.
  2. A MIPS intensive task of zipping and unzipping a file.

This data is presented in Figure 2. The different operations are clearly marked in this figure.

Current profile for different operations per supply rail. Figure 2. Current profile for different operations per supply rail.

The breakdown of the average power consumptions for each operation per supply rail is presented in Table 1.

Table 1. Current and Power Consumption per Rail Voltage and per Operation

  Current Consumption on Each Voltage Rail (mA)  
  RAIL VOLTAGE 1.0V 1.8V 3.3V Total Power for Each Operation (mW)
Operation ROM Loading U-Boot 328.0 1.3 126.0 746
U-Boot Loading Kernel 422.0 30.8 147.0 961
Kernel Booting 420.0 33.3 105.0 826
Smartcard Transaction 410.0 22.7 110.0 814
Zip and Unzip Operations 421.0 39.5 109.0 852
STOP Mode 52.0 2.6 52.0 228

Also in Figure 3, Figure 4, and Figure 5, the histograms of the current consumption are presented for each voltage rail.

1V rail current histogram. Figure 3. 1V rail current histogram.

1.8V rail current histogram. Figure 4. 1.8V rail current histogram.

3.3V rail current histogram. Figure 5. 3.3V rail current histogram.

Conclusion and Observations

  • Turning on the PLL increases the 1.0V rail current from 330mA to 409mA.
  • 1.0V rail current can peak to 450mA during the kernel loading and booting.
  • Smart card operation has a very little effect on the power rails.
  • Extensive LPDDR exchange during zip and unzip operation can increase the 1.8V rail current from 22mA to 40mA.
  • The 3.3V rail is mainly plateaued at 110mA during these tests. Obviously the current can fluctuate from 100mA to 175mA during load operations from NAND flash.
  • STOP mode power consumption is around 230mW