Choosing the Optimal Clock Mode for MAX116xx, MAX123x, and MAX103x SAR ADCs

By: Mohamed Ismail

Abstract: The MAX116xx, MAX103x, and MAX123x families of low-power, multichannel, 300ksps SAR ADCs have configurable clock modes that enable flexibility when interfacing with a SPI master. This application note discusses the advantages of each clock mode and provides timing examples for each mode.