# Simulation Shows How Real Op Amps Can Drive Capacitive Loads

Abstract: Electrical engineers designing analog electronics commonly have to drive a capacitive load with an operational amplifier that cannot quite handle the required capacitance. Common approaches to handling this situation have limitations that are not always understood. Using simulation, we show these limitations and how to overcome them.

**Associated simulation files are available for download (requires either a purchased or demo version of TINA**

^{®}, a commercial Spice-based simulator, which can be obtained at www.tina.com).*EDN*, April 28, 2013.

## From Ideal to Real: Starting with the Basics

**Figure 1**shows a simple “ideal” op-amp circuit with a gain of -1 driving a 1µF capacitive load.

*Figure 1. Basic op amp driving a capacitive load.*

*Figure 2. The Figure 1 circuit with op amp output resistance added.*

_{OUT}and C1. The resulting pole frequency is:

f_{p} = 1/2πRC = 2.122kHz |
(Eq. 1) |

## Don’t Get “Lost In Spice”

## Let’s Get Simulating

**Note**: You can download the simulation files (ZIP) (requires either a purchased or demo version of TINA

^{®}, a commercial Spice-based simulator, which can be obtained at www.tina.com) for all of the following circuits.

**Figure 3**shows the table of adjustable parameters.

*Figure 3. Parameterized op amp model.*

- Open loop gain: 200k (106dB)
- Dominant pole: 5Hz
- Second pole: 10MHz
- Output resistance: 75Ω

**Figure 4**shows the open-loop gain and phase of our op amp.

*Figure 4. Op amp open-loop gain and phase.*

## How Does It Work with that Capacitive Load?

**Figure 5**shows our parameterized op amp in the same circuit as Figure 1 but with some new components added, specifically Vt, Ct, and Lt.

*Figure 5. Capacitive load circuit with components to measure the loop.*

**Figure 6**).

*Figure 6. Bode plot of the loop gain for the circuit in Figure 5.*

## Making It Stable

**Figure 7**.

*Figure 7. Adding a small isolation resistor isolates the op amp from the capacitance and increases stability.*

Z_{OUT}(s) = R_{3}/(1 + C_{2}R_{3}s) |
(Eq. 2) |

**Figure 8**shows the modified schematic.

*Figure 8. Adding the Z-Meter to measure the output impedance.*

**Figure 9**shows this impedance plotted like a voltage transfer function, displaying a single-pole response with a pole frequency of 3.18kHz.

*Figure 9. The output impedance of the Figure 8 circuit.*

## Adding a Second Feedback Loop

**Figure 10**shows this configuration.

*Figure 10. A dual feedback path is created by adding another capacitor, C1.*

_{IN}to V

_{OUT}. The transfer function in the Laplace domain is fairly easy to determine, but there is an interesting feature of TINA: symbolic analysis. As long as we use an ideal op amp, TINA can provide the transfer function equation.

**Figure 11**shows what the AC transfer symbolic analysis function returns:

*Figure 11. Symbolic analysis results.*

(Eq. 3) |

**Figure 12**.

*Figure 12. The Bode plot of the transfer function.*

## Not So Fast, Buddy—Put that Beer Down!

**Figure 13**includes the same additional components used in Figure 5 that are needed to measure the closed loop.

*Figure 13. Modified circuit for loop measurement.*

**Figure 14**and indicate that we have more than 50° phase margin.

*Figure 14. Loop gain plot shows over 50° phase margin.*

**Figure 15**.

*Figure 15. Measuring the output impedance of the dual-loop design.*

**Figure 16**.

*Figure 16. Output impedance for the dual-loop circuit.*

_{OUT}as the input. The output of the op amp is thus:

(Eq. 4) |

_{OUT}- V

_{OPAMP_OUTPUT}, which means that the current through R3 is:

(Eq. 5) |

(Eq. 6) |

(Eq. 7) |

(Eq. 8) |

## Examining This Effect over a Wider Range of Conditions

**Figure 17**plots the output impedance for 20 different logarithmically spaced values for C1 from 500pF to 5µF.

*Figure 17. Output impedance by varying C1.*

_{OUT}= 50Ω. Keep in mind, however, that this is the ideal case with a perfect op amp that has infinite gain at all frequencies. It is instructive to examine such an ideal case to isolate this behavior from other effects. Shortly, we will look at more realistic cases.

**Figure 18**shows both amplitude and phase of the frequency response of our circuit with C1 varying.

*Figure 18. Frequency response of the Figure 15 circuit as C1 varies from 100pF to 1µF.*

## Getting a Bit More Real

**Figure 19**is the equivalent of Figure 17 using the parameterized op amp with a GBWP of 1MHz.

*Figure 19. Z*

_{OUT}with a 1MHz GBWP op amp.**Figure 20**.

*Figure 20. Frequency response with 1MHz GBWP op amp.*

**Figure 21**shows the output impedance using an op amp with a GBWP of 10MHz.

*Figure 21. Increasing GBWP to 10MHz.*

## There Is a Real Application for All This

**Figure 22**shows the addition of such a circuit. Note that we need not worry about the voltage drop across the base-emitter PN junction, as our DC feedback loop corrects for it.

*Figure 22. Adding a follower.*

**Figure 23**shows the simulated output impedance using our Z-Meter.

*Figure 23. Output impedance with the added follower.*

**Figure 24**is the output impedance plot with this change to R4. Notice that the peak impedance has been cut nearly in half.

*Figure 24. Output impedance with twice the emitter current.*

**Figure 25**demonstrates a well-behaved frequency response.

*Figure 25. Transfer function frequency response of final circuit.*

**Figure 26**. We can see that there is nearly 90° of phase margin and the curves are well behaved, so this would appear to be a very stable design.

*Figure 26. The loop gain of the final circuit indicates a stable design.*