# Selecting External Components and Compensation for Automotive Step-Up DC-DC Regulator with Preboost Reference Design

Abstract: In this application note, the parameters and calculations needed in the selection of external components for optimal performance of the MAX16990/MAX16992 in boost configurations are reviewed. Next, the selection of compensation components is discussed and a general method that can be extrapolated to compensate any boost regulator is offered. A calculator is provided to help the user in the selection of external components, compensation design, and the evaluation of power-supply performance. A reference design, showing how the devices can be used in an automotive preboost application, is discussed as is the optimal layout for this boost regulator.

## Introduction

## Selection of External Components

### Parameters for Choosing External Components

- Switching frequency (f
_{SW}) - Output voltage (V
_{OUT}) - Output current range (I
_{OUTMIN}and I_{OUTMAX}) - Input voltage range (V
_{INMIN}and V_{INMAX})

(Eq. 1) | |

(Eq. 2) |

_{MIN}and D

_{MAX}) where the regulator operates. This can be determined with the following two equations:

(Eq. 3) | |

(Eq. 4) |

_{D}is the forward voltage of the rectifier diode, R

_{DS(ON)}the drain-source resistance of the nMOS when turned on, and R

_{SENSE}the sense resistor. Because we have not chosen R

_{SENSE}yet, ignore this term in the equations for now. We will make a more accurate estimate of the duty cycle range later.

### Inductor

_{C}) as calculated with Equation 5:

(Eq. 5) |

_{C}assumes its maximum value for D = 33% if it is in the calculated duty cycle range; otherwise choose the maximum value for L

_{C}between the ones calculated at the maximum and minimum duty cycles.

(Eq. 6) |

(Eq. 7) |

_{C}, the LIR factor is 2. Further increasing L reduces the LIR factor. The selected inductor has to have a saturation current higher than its peak current, which is:

(Eq. 8) |

**Figure 1**illustrates the inductor current shape during the switching period.

*Figure 1. Inductor current of the boost regulator.*

_{OUT}) plus the drop on the rectifier diode (V

_{D}), and the maximum reverse voltage across the rectifier diode is equal to the output voltage (V

_{OUT}).

### Sense Resistor

_{SENSE}). The device triggers the current limit when the voltage on the ISNS pin reaches 212mV (min). A portion of this voltage is due to the drop on the sense resistor and another portion to the drop on the slope resistor (R

_{SLOPE}), which is used for slope compensation. To leave 100mV of room for slope compensation, it is initially recommended for R

_{SENSE}to generate a voltage drop of 112mV at the current limit threshold. In Equation 9, R

_{SENSE}is calculated with a current limit threshold 20% higher than the peak inductor current.

(Eq. 9) |

### Output Capacitor

_{OUT}) and its related ESR is very important to minimize output voltage ripple.

_{OUT_RIPPLE}) is equally distributed between the voltage drop, which is due to the capacitor discharging during off-time, and the ESR voltage drop.

(Eq. 10) | |

(Eq. 11) |

## Compensation

**Figure 2**for an overview of the boost regulation loop, which is composed of the power stage (A(f)) and the feedback stage (B(f)).

*Figure 2. Boost regulator small-signal model.*

_{COMP}, C

_{COMP}, C

_{COMP2}, and R

_{SLOPE}), it is necessary to describe the loop response in the frequency domain and evaluate its stability. The regulation loop can be divided into two stages.

_{OUT}), and the load resistor (R

_{LOAD}). The frequency response of this stage is described by Equation 12:

(Eq. 12) |

(Eq. 13) |

(Eq. 14) |

(Eq. 15) |

(Eq. 16) |

(Eq. 17) |

AFB = V_{REF}/V_{OUT} |
(Eq. 18) |

AEA = gm × R_{OUT} |
(Eq. 19) |

_{OUT}its output.

_{COMP}and R

_{COMP}:

(Eq. 20) | |

(Eq. 21) |

_{COMP2}):

(Eq. 22) |

Loop(f) = A(f) × B(f) | (Eq. 23) |

(Eq. 24) |

_{n}is the positive inductor current ramp during on-time multiplied by the sense resistor (voltage ramp on R

_{SENSE}):

(Eq. 25) |

_{e}is the slope compensation ramp multiplied by R

_{SENSE}plus R

_{SLOPE}:

S_{e} = I_{COMP} × f_{SW} × (R_{SLOPE} + R_{SENSE}), I_{COMP} = 50µA |
(Eq. 26) |

_{SLOPE}must have a Q factor between zero and one in all operating conditions.

_{SLOPE}higher than the value shown in Equation 27 ensures a Q factor between 0 and 1 in all operating conditions:

(Eq. 27) |

_{SLOPE}has been selected, it is possible to calculate the value of the real minimum current limit using Equation 28:

(Eq. 28) |

_{SENSE}and R

_{SLOPE}accordingly until the desired value is reached.

_{C,TARGET}), which has to be lower than f

_{SW}/10 and f

_{Z,RHP}/10. Initially, we assume that the zero due to the output capacitor ESR (f

_{Z,ESR}) is ten times higher than f

_{C,TARGET}. Under this assumption, the closed-loop frequency response can be approximated as a simple two poles and one zero system frequency response.

(Eq. 29) | |

DC_{GAIN} = ACM × AFB × AEA |
(Eq. 30) |

_{GAIN}, two cases can be considered.

(Eq. 31) |

**Figure 3**), place the error amplifier pole after the load pole :

(Eq. 32) |

(Eq. 33) |

*Figure 3. Bode diagram of the amplitude of the closed-loop response, case 1.*

(Eq. 34) |

**Figure 4**), place the error amplifier pole before the load pole:

(Eq. 35) |

(Eq. 36) |

*Figure 4. Bode diagram of the amplitude of the closed-loop response, case 2.*

_{COMP}to increase the crossover frequency and the phase margin.

_{COMP2}) corresponding to the ESR zero:

(Eq. 37) |

## Reference Design

f_{SW} |
2.2MHz |

V_{IN} |
3.5V to 6V |

V_{OUT} |
8V |

I_{OUT} |
1A to 2A |

V_{OUT_RIPPLE} |
50mV |

(Eq. 38) | |

(Eq. 39) |

(Eq. 40) |

_{DS(ON)}of this transistor is 15mΩ with a V

_{GS}= 5V (the gate-source voltage of the MAX16992).

_{SENSE}for now:

(Eq. 41) | |

(Eq. 42) |

(Eq. 43) |

_{OUT}= 1A.

_{R}= 18A, I

_{SAT}= 20A). With this inductor, when the input voltage is at its minimum (and the input current at its maximum):

(Eq. 44) |

(Eq. 45) |

(Eq. 46) |

_{SENSE}.

_{OUT}are:

(Eq. 47) | |

(Eq. 48) |

_{SLOPE}:

(Eq. 49) |

(Eq. 50) |

_{GAIN}, load pole frequency, and the right-half plane zero frequency are:

DC_{GAIN} = ACM × AFB × AEA = 91.6dB |
(Eq. 51) |

(Eq. 52) | |

(Eq. 53) |

(Eq. 54) |

_{Z,RHP}/10 = 25.9kHz.

(Eq. 55) |

_{COMP}target becomes:

(Eq. 56) |

_{COMP}target is:

(Eq. 57) |

_{COMP2}:

(Eq. 58) |

(Eq. 59) | |

(Eq. 60) | |

(Eq. 61) |

_{CROSS}) and phase margin (PM).

f_{CROSS} = 26.3kHz |
(Eq. 62) |

PM = 45° | (Eq. 63) |

**Figure 5**and

**Figure 6**.

*Figure 5. Loop gain.*

*Figure 6. Loop phase.*

Designation | Description |

N | Fairchild FDS5670 nMOS |

D | Diodes Inc. B3x0-13-F |

L | Würth Elektronik 744314047 |

C_{OUT} |
Murata GRM32ER61C476K |

*Figure 7. Schematic of reference design.*

## Layout Recommendation

- Place all power components on the same side of the board.
- Keep the AC paths as short as possible. During on-time, the AC path is composed of C
_{IN}, an inductor, nMOS, R_{SENSE}, and GND. During off-time, the AC path is composed of C_{IN}, an inductor, a diode, C_{OUT}, and GND. - Keep the switching node (LX) as compact as possible.
- Do not route the path between the DRV pin and the gate of the nMOS with the minimum width. This net commutes at the switching frequency and has to carry the current necessary to drive the nMOS. If vias are necessary, route the net to an internal layer.
- Connect the C
_{SUP}and C_{PVL}capacitors directly to the IC, as close as possible without using vias. - Use a Kelvin connection between R
_{SENSE}and R_{SLOPE}, and between R_{SLOPE}and the ISNS pin. - Use a Kelvin connection between OUT and RTOP. Keep the FB node as close as possible to the FB pin of the IC.
- Use two separate GNDs as indicated on the schematic: PGND for power components and AGND for the signal circuitry and the EP of the MAX16992. Use a single-point connection between PGND and AGND, as close as possible to the EP.

**Figure 8**through

**Figure 12**.

*Figure 8. Reference design layout, top layer.*

*Figure 9. Reference design layout, inner layer 1.*

*Figure 10. Reference design layout, inner layer 2.*

*Figure 11. Reference design layout, back layer.*

*Figure 12. Reference design, 3D view.*