APPLICATION NOTE 4735

Quick Reference Guide for Programming the DS1873 SFP+ Controller

By: Hrishikesh Shinde

Abstract: The DS1873 enhanced small form factor pluggable (SFP+) controller with digital laser diode driver (LDD) interface allows various programming options to configure the alarms, warnings, lookup tables (LUTs), and other functions. This programmability necessitates a large register memory map. The application note provides an alternate view of the register map, which is convenient when programming the device.

Introduction

The DS1873 controls and monitors all functions for small form factor (SFF), small form factor pluggable (SFP), and SFP+ modules including all SFF-8472 functionality. Six ADC channels monitor VCC, temperature, and four external monitor inputs (MON1–MON4) can be used to meet all monitoring requirements. Two digital-to-analog (DAC) outputs with temperature-indexed lookup tables (LUTs) are available for additional monitoring and control functionality. To monitor these many functions, the DS1873 controller needs a large register memory map. This application note presents an alternate view of that register map.

Memory Map of the DS1873

The DS1873 features nine separate memory tables that are internally organized into eight byte rows.

The Lower Memory is addressed from 00h to 7Fh. It contains alarm and warning thresholds, flags, masks, several control registers, password entry area (PWE), and the Table Select byte.

Table 01h primarily contains user EEPROM (with PW1 level access), as well as alarm and warning enable bytes.

Table 02h is a multifunction space that contains configuration registers, scaling and offset values, passwords, interrupt registers, and other miscellaneous control bytes.

Table 04h contains a temperature-indexed LUT for controlling the modulation voltage. The modulation LUT can be programmed in 2°C increments over the -40°C to +102°C range.

Table 05h is empty by default. It can be configured to contain the alarm and warning enable bytes from Table 01h, Registers F8h–FFh, with the MASK bit enabled (Table 02h, Register 89h). In this case, Table 01h will be empty.

Table 06h contains a temperature-indexed LUT that allows the automatic power control (APC) set point to change as a function of temperature to compensate for Tracking Error (TE). The APC LUT has 36 entries that determine the APC setting in 4°C windows between -40°C to +100°C.

Table 07h contains a temperature-indexed LUT for controlling DAC1. The LUT has 72 entries that determine the DAC setting in 4°C windows between -40°C to +100°C.

Table 08h contains a temperature-indexed LUT for controlling DAC2. The LUT has 36 entries that determine the DAC setting in 4°C windows between -40°C to +100°C.

Auxiliary memory (device A0h) contains 256 bytes of EEPROM accessible from address 00h–FFh. The auxiliary memory is selected with the device address of A0h.

Refer to the tables below for more complete details of each byte's function and for read/write permissions for each byte.

Shadowed EEPROM

Many nonvolatile memory locations (see the Register reference section below) are actually shadowed EEPROM and are controlled by the SEEB bit in Table 02h, Register 80h.

The DS1873 incorporates shadowed EEPROM memory locations for key memory addresses that can be written many times. By default, the shadowed EEPROM bit, SEEB, is not set and these locations act as ordinary EEPROM. By setting SEEB these locations function like SRAM cells, which allow an infinite number of write cycles without concern for wearing out the EEPROM. Using the SEEB bit also eliminates the requirement for the EEPROM write time, tWR. Because changes made with SEEB enabled do not affect the EEPROM, these changes are not retained through power cycles. The power-on value is the last value written with SEEB disabled. The SEEB function can be used to limit the number of EEPROM writes during calibration, or to change the monitor thresholds periodically during normal operation. This helps reduce the number of times that EEPROM is written. The Memory Map description below indicates which locations are shadowed EEPROM.

DS1873 Memory Map

DS1873 memory map
More detailed image
(PDF, 200kB)

Register Reference

The following tables provide an easy reference to the Lower Memory, and Tables 01h and 02h. For description of the functionality for each bit, please refer to the corresponding register in the data sheet. Tables 04h through 08h are LUTs that do not require a separate reference and, hence, are not included here. Please refer to the data sheet for detailed information about these tables.

Note: RSVD is used as an acronym for "reserved."

Lower Memory
Register Name Address (h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TEMP ALARM HI
TEMP WARN HI
00, 04 S 26 25 24 23 22 21 20
01, 05 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8
TEMP ALARM LO
TEMP WARN LO
02, 06 S 26 25 24 23 22 21 20
03, 07 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8
VCC ALARM HI
VCC WARN HI
MON1–4 ALARM HI
MON1–4 WARN HI
08, 0C, 10, 14, 18, 1C, 20, 24, 28, 2C 215 214 213 212 211 210 29 28
09, 0D, 11, 15, 19, 1D, 21, 25, 29, 2D 27 26 25 24 23 22 21 20
VCC ALARM LO
VCC WARN LO
MON1–4 ALARM LO
MON1–4 WARN LO
0A, 0E, 12, 16, 1A, 1E, 22, 26, 2A, 2E 215 214 213 212 211 210 29 28
0B, 0F, 13, 17, 1B, 1F, 23, 27, 2B, 2F 27 26 25 24 23 22 21 20
PW2 EE 30–5F EE EE EE EE EE EE EE EE
TEMP VALUE 60 S 26 25 24 23 22 21 20
61 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8
VCC VALUE
MON1–4 VALUE
62, 64, 66, 68, 6A 215 214 213 212 211 210 29 28
63, 65, 67, 69, 6B 27 26 25 24 23 22 21 20
RESERVED 6C, 6D 0 0 0 0 0 0 0 0
STATUS 6E TXDS TXDC IN1S RSELS RSELC TXF RXL RDYB
UPDATE 6F TEMP RDY VCC RDY MON1 RDY MON2 RDY MON3 RDY MON4 RDY RSVD RSSIR
ALARM3 70 TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
ALARM2 71 MON3 HI MON3 LO MON4 HI MON4 LO RSVD RSVD RSVD TXFINT
ALARM1 72 RSVD RSVD RSVD RSVD HBAL RSVD TXP HI TXP LO
ALARM0 73 LOS HI LOS LO RSVD RSVD BIAS MAX RSVD RSVD RSVD
WARN3 74 TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
WARN2 75 MON3 HI MON3 LO MON4 HI MON4 LO RSVD RSVD RSVD RSVD
RESERVED 76–7A RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
PASSWORD ENTRY 7B 231 230 229 228 227 226 225 224
7C 223 222 221 220 219 218 217 216
7D 215 214 213 212 211 210 29 28
7E 27 26 25 24 23 22 21 20
TABLE SELECT 7F 27 26 25 24 23 22 21 20

Table 01h
Register Name Address (h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
EEPROM 80-BF EE EE EE EE EE EE EE EE
EEPROM C0-F7 EE EE EE EE EE EE EE EE
ALARM EN3 F8 TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
ALARM EN2 F9 MON3 HI MON3 LO MON4 HI MON4 LO RSVD RSVD RSVD RSVD
ALARM EN1 FA RSVD RSVD RSVD RSVD HBAL RSVD TXP HI TXP LO
ALARM EN0 FB LOS HI LOS LO RSVD RSVD BIAS MAX RSVD RSVD RSVD
WARN EN3 FC TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
WARN EN2 FD MON3 HI MON3 LO MON4 HI MON4 LO RSVD RSVD RSVD RSVD
RESERVED FE-FF RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Table 02h
Register Name Address (h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
MODE 80 SEEB RSVD DAC1 EN DAC2 EN AEN MOD EN APC EN BIAS EN
T INDEX 81 27 26 25 24 23 22 21 20
MOD DAC VALUE 82 0 0 0 0 0 0 0 28
83 27 26 25 24 23 22 21 20
DAC1 VALUE 84 0 0 0 0 0 0 0 28
85 27 26 25 24 23 22 21 20
DAC2 VALUE 86 0 0 0 0 0 0 0 28
87 27 26 25 24 23 22 21 20
UPDATE RATE 88 SEE SEE SEE SEE APC_SR3 APC_SR2 APC_SR1 APC_SR0
CNFGA 89 LOSC RSVD INV LOS ASEL MASK INVRSOUT RSVD RSVD
CNFGB 8A IN1C INVOUT1 RSVD RSVD RSVD ALATCH QTLATCH WLATCH
CNFGC 8B XOVREN RSVD TXDM34 TXDFG TXDFLT TXDIO RSSI_FC RSSI_FF
DEVICE ADDR 8C 27 26 25 24 23 22 21 20
RIGHT SHIFT2 8D RSVD RSVD RSVD RSVD RSVD MON3C2 MON3C1 MON3C0
RIGHT SHIFT1 8E RSVD MON12 MON11 MON10 RSVD MON22 MON21 MON20
RIGHT SHIFT0 8F RSVD MON3F2 MON3F1 MON3F0 RSVD MON42 MON41 MON40
XOVER COARSE 90 215 214 213 212 211 210 29 28
91 27 26 25 24 23 22 21 0
VCC SCALE
MON1–2 SCALE
MON3 F SCALE
MON4 SCALE
MON3 C SCALE
92, 94, 96, 98, 9A, 9C 215 214 213 212 211 210 29 28
93, 95, 97, 99, 9B, 9D 27 26 25 24 23 22 21 20
RESERVED 9E–9F RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
XOVER FINE A0 215 214 213 212 211 210 29 28
A1 27 26 25 24 23 22 21 0
VCC OFFSET
MON1–2 OFFSET
MON3 F OFFSET
MON4 OFFSET
MON3 C OFFSET
A2, A4, A6, A8, AA, AC S S 215 214 213 212 211 210
A3, A5, A7, A9, AB, AD 29 28 27 26 25 24 23 22
INTERNAL TEMP OFFSET AE S 28 27 26 25 24 23 22
AF 21 20 2-1 2-2 2-3 2-4 2-5 2-7
PW1 B0 231 230 229 228 227 226 225 224
B1 223 222 221 220 219 218 217 216
B2 215 214 213 212 211 210 29 28
B3 27 26 25 24 23 22 21 20
PW2 B4 231 230 229 228 227 226 225 224
B5 223 222 221 220 219 218 217 216
B6 215 214 213 212 211 210 29 28
B7 27 26 25 24 23 22 21 20
LOS RANGING B8 RSVD HLOS2 HLOS1 HLOS0 RSVD LLOS2 LLOS1 LLOS0
COMP RANGING B9 RSVD HBIAS2 HBIAS1 HBIAS0 RSVD APC2 APC1 APC0
IBIASMAX BA 29 28 27 26 25 24 23 22
ISTEP BB 28 27 26 25 24 23 22 21
HTXP BC 27 26 25 24 23 22 21 20
LTXP BD 27 26 25 24 23 22 21 20
HLOS BE 27 26 25 24 23 22 21 20
LLOS BF 27 26 25 24 23 22 21 20
PW_ENA C0 RWTBL78 RWTBL1C RWTBL2 RWTBL1A RWTBL1B WLOWER WAUXA WAUXB
PW_ENB C1 RWTBL46 RTBL1C RTBL2 RTBL1A RTBL1B WPW1 WAUXAU WAUXBU
RESERVED C2–C5 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
POLARITY C6 RSVD RSVD RSVD RSVD MODP BIASP DAC1P DAC2P
TBLSELPON C7 27 26 25 24 23 22 21 20
MAN BIAS C8 0 0 0 0 0 0 0 28
C9 27 26 25 24 23 22 21 20
MAN_CNTL CA RSVD RSVD RSVD RSVD RSVD RSVD RSVD MAN_CLK
BIAS DAC CB RSVD RSVD RSVD RSVD RSVD RSVD 29 28
CC 27 26 25 24 23 22 21 20
RESERVED CD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
DEVICE ID CE 0 1 1 1 0 0 1 1
DEVICE VER CF
DEVICE VERSION
APC DAC D0 27 26 25 24 23 22 21 20
HBIAS DAC D1 27 26 25 24 23 22 21 20
RESERVED D2–D7 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
EMPTY D8–FF
EMPTY

Table 04h: Registers 80h–C7h: MODULATION LUT
Table 04h, Registers F8h–FFh: MOD OFFSET LUT

Table 06h: Registers 80h–A3h: APC LUT
Table 06h, Registers F8h–FFh: HBIAS LUT

Table 07h: Registers 80h–C7h: DAC1 LUT
Table 07h, Registers F8h–FFh: DAC1 OFFSET LUT

Table 08h: Registers 80h–A3h: DAC2 LUT
Table 08h, Registers F8h–FFh: DAC2 OFFSET LUT