Keywords: jitter, optical receivers, timing jitter, edge speed, aberrations, optical dispersion, attenuation, clock recovery, sdh/sonet receivers, transimpedance preamplifiers, limiting postamplifiers, dispersion, amplifiers, cdr, clock recovery data, cdr bloc
Figure 1. Eye diagram with and without timing jitter
Optical receivers, incorporating transimpedance preamplifiers and limiting postamplifiers, can significantly clean up the effects of dispersion and attenuation. In addition, these amplifiers can provide fast transitions with minimal aberrations to the subsequent clock/data recovery (CDR) blocks. However, these stages also add distortions to the midpoint crossing, contributing to timing jitter. Timing jitter is one of the most critical technical issues to consider when developing optical receivers and CDR circuits.
A better understanding of the different sources of jitter helps in the design and application of optical receiver modules and integrated CDR solutions. SDH/SONET specifications are well defined regarding the amount of jitter tolerance allowed at the inputs of optical receivers, as well as jitter-peaking requirements, but they do little to define the different sources of jitter. The jitter that must be tolerated at an optical receiver input involves three significant sources, all of which are present to varying degrees in typical receiver systems:
1) Random jitter (RJ)
2) Pattern-dependent jitter (PDJ)
3) Pulse-width distortion (PWD)
Figure 2. Random jitter on edge transition
3 Pattern-Dependent Jitter (PDJ)
PDJ results from wide variations in the number of consecutive bits contained in NRZ data streams working against the bandwidth requirements of the receiver (Figure 3). The location of the lower -3dB cutoff frequency is important and must be set to pass the low frequencies associated with long, consecutive bit streams. AC-coupling is common in optical receiver design.
Figure 3. Pattern-dependent jitter due to low-frequency cutoff
When using a limiting preamplifier with a highpass frequency response, select the input AC-coupling capacitor into the postamplifier, CAC, in order to provide a low-frequency cutoff (fC) one decade lower than the preamplifier low-frequency cutoff. As a result, the PDJ is dominated by the low-frequency cutoff of the preamplifier.
When using a preamplifier without a highpass response, the following equation provides a good starting point for choosing CAC into the postamplifier:
where tL = duration of the longest run of consecutive bits of the same value (seconds); Rin = input resistance of the postamplifier; PDJ = maximum allowable pattern-dependent jitter, peak-to-peak (seconds); and BW = typical system bandwidth, normally 0.6 to 1.0 times the data rate (hertz). If the PDJ is still larger than desired, continue increasing the value of CAC. Note that to maintain stability, it is important to keep the low-frequency cutoff well below the corner frequency associated with the postamplifier.
PDJ can also be present due to insufficient high-frequency bandwidth (Figure 4). If the amplifiers are not fast enough to allow for complete transitions during single-bit patterns, or if the amplifier does not allow adequate settling time, high-frequency PDJ can result.
Figure 4. Pattern-dependent jitter due to high-frequency rolloff
4 Pulse-Width Distortion (PWD)
Finally, PWD occurs when the midpoint crossing of a 0-1 transition and a 1-0 transition do not occur at the same level (Figure 5). DC offsets and nonsymmetrical rising and falling edge speeds both contribute to PWD. For a 1-0 bit stream, calculate PWD as follows:
Figure 5. Pulse-width distortion