HFAN-04.5.5 Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers

By: Sharon Wang

Abstract: This application note discusses the effects of power-supply noise interference on PLL-based clock generators. It describes several measurement techniques for evaluating the resulting DJ (deterministic jitter). Relationships are derived outlining how frequency-domain spur measurements can be used to evaluate timing jitter behavior. Laboratory bench-test results are used to compare the approaches, and demonstrate how to reliably assess the PSNR (power-supply noise rejection) performance of a reference clock generator.

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APP 4461:
APPLICATION NOTE 4461,AN4461, AN 4461, APP4461, Appnote4461, Appnote 4461