APPLICATION NOTE 4272

Overview of the MAX11040K 24-Bit Simultaneous-Sampling, Sigma-Delta ADC

By: Sohail Mirza

Abstract: This application note highlights the key features of the MAX11040K simultaneous-sampling sigma-delta ADC. The article will discuss 4-channel simultaneous sampling; the ability to program phase delays individually for each channel; cascading up to eight devices; and the operation of the active-low FAULT and OVERFLOW signals. Example test data, generated with device's evaluation (EV) kit, will be shown.

Four-Channel Simultaneous Sampling

The MAX11040K integrates four 24-bit, sigma-delta ADCs to enable 4-channel simultaneous sampling. Unlike multiplexed-channel sigma-delta ADCs that do not maintain phase integrity, the MAX11040K not only records the phase information but also allows the user to program phase on individual channels.

Figure 1 shows same analog signal applied (zero phase delay) to all four ADC inputs, and the resulting sampled data.

Figure 1. The same sine-wave signal was applied to the four inputs of the MAX11040K. Simultaneous outputs are shown at right.
Figure 1. The same sine-wave signal was applied to the four inputs of the MAX11040K. Simultaneous outputs are shown at right.

Individual Phase-Delay Programming for Each Channel

Users can independently program phase delay for each ADC channel with a maximum of 333µs delay in 1.33µs steps. By programming phase delays into the ADC channels, the users can null out inherent phase delays caused by filters, delay lines, etc., in their signal path. The delay step size is also smaller than the data rate, thus allowing the user a resolution not available after acquisition.

Figure 2 shows the sampled output when zero phase delay is programmed and when varying phase delays are programmed. In both cases, all four inputs are tied to the same signal source.

Figure 2. The same sine-wave signal was applied to the four inputs of the MAX11040K. Figure 2A shows the simultaneous output from the four channels when zero phase delay was programmed. Figure 2B shows the simultaneous output from the four channels when varying phase delays were programmed.
Figure 2. The same sine-wave signal was applied to the four inputs of the MAX11040K. Figure 2A shows the simultaneous output from the four channels when zero phase delay was programmed. Figure 2B shows the simultaneous output from the four channels when varying phase delays were programmed.

Cascade up to 8 Devices

If four channels are not sufficient for an application, one can cascade up to eight MAX11040K devices together to enable 32 channels of simultaneous sampling. This feature is ideal for applications such as EEG that requires multiple simultaneous sampling channels for brain-wave monitoring.

Figure 3 shows the device setup.
  • The active-low CASCOUT signal from the first device is fed into active-low CASCIN of the second device. The setup is similar for the second device to the third and following devices. Finally, active-low DRDYOUT from the last device signals that the data is ready from all devices.
  • The CLKOUT signal from the first device is fed into the XIN of all the other devices.
  • Active-low FAULT and active-low OVRFLW are in a wired-OR arrangement.
Figure 3. Diagram of the setup for cascading up to 8 MAX11040K devices.
Figure 3. Diagram of the setup for cascading up to 8 MAX11040K devices.

FAULT and OVERFLOW Signals

The MAX11040K generates active-low OVERFLOW and active-low FAULT signals whenever the input goes above ±0.88% of VREF or above 6V, respectively. This feature is important for generating an alarm on saturation or if the application needs overvoltage (OV) protection.

Figure 4 illustrates the process for a fast-moving input; Figure 5 illustrates the process for a slow-moving input. For the fast signals, the transition on the active-low OVERFLOW and FAULT signals is almost simultaneous. One should note that there is a latent period from when the signal crosses the threshold and before the active-low OVERFLOW and FAULT signals go low. There is a similar recovery time before the signals return high.

Figure 4. High-frequency analog input OV detection and recovery for a fast-moving input.
Figure 4. High-frequency analog input OV detection and recovery for a fast-moving input.

Figure 5. High-frequency analog input OV detection and recovery for a slow-moving input.
Figure 5. High-frequency analog input OV detection and recovery for a slow-moving input.

Example Data

The following example data was generated with the MAX11040K EV kit.

Simultaneous Sampling, Programmable Phase Delay, and Cascadable Device Setup

Figure 6 shows the block diagram of two ADCs. The settings were programmed for various phase delays. An AC signal of 4VP-P running at 120Hz was provided to the 8 inputs (four inputs for each device). The phase delay for each channel was programmed with the following codes:

CH1 0 0 0µs
CH2 36 36 46.88µs
CH3 2 × 36 72 93.75µs
CH4 3 × 36 108 140.62µs
CH1 4 × 36 144 187.50µs
CH2 5 × 36 180 234.38µs
CH3 6 × 36 216 281.25µs
CH4 7 × 36 252 328.12µs

Figure 6. Two MAX11040K ADCs are shown with the various phase delays applied to the signal.
Figure 6. Two MAX11040K ADCs are shown with the various phase delays applied to the signal.

Figures 7 and 8 show the captured data from the two MAX11040K devices in Figure 6. One can see that, although the same signal was applied to all the inputs, the resulting waveform is out of phase due to the programmed phase delay.

Figure 7.The data that resulted from the dual ADC setup in Figure 6.
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Figure 7. The data that resulted from the dual ADC setup in Figure 6.

Figure 8. A zoomed-in view of Figure 7.
More detailed image
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Figure 8. A zoomed-in view of Figure 7.

Fault and Overflow Detection (Application Assistance)

If a designer wants to use active-low OVERFLOW or active-low FAULT as interrupt signals, then either an external D flip flop or an internal latch is needed in the hardware. The signals will become latched when the active-low OVERFLOW or active-low FAULT goes low on the active-low SD pin. The interrupt controller can reset the signals by driving the active-low RD pin low (Figure 9).

Figure 9. Latching OVERFLOW or FAULT signals.
Figure 9. Latching OVERFLOW or FAULT signals.

With all the key features mentioned, MAX11040K is an ideal candidate for:
  • Three phase plus neutral lines for power measurement and monitoring
    By using voltage and current transformers to bring down the voltage to acceptable levels, two MAX11040Ks can be cascaded to monitor three phases plus a neutral voltage and current signals. Although a sigma-delta ADC with 24-bit accuracy, the MAX11040K has sufficient sampling rates to monitor greater than 24 harmonics (industry standard). With ENOB of nearly 18, electrical noise as well as large transients can be captured to help determine the quality of power. Phase shifts that can create offsets in your power-factor calculations can easily be compensated by programming phase delays. At the same time OVERFLOW and FAULT can be easily detected and captured.

    Figure 10

  • EEG/EKG signal monitoring

    Figure 11

    With a high dynamic range, a second gain stage can be eliminated to reduce component count and cost, and improve reliability. Having a sigma-delta architecture with a fifth-order modulator, the MAX11040K provides excellent noise performance compared to SAR and other architectures. It also provides 32 channels with phase adjust to monitor many parts of the brain simultaneously.

Related Parts
MAX11040K Free Sample
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APP 4272:
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