are high-precision, low-cost signal conditioners that can be operated in two modes: digital mode for system-level manufacturing and analog mode for normal operation. The MAX1452/MAX1455 contain a power-on reset (POR) circuit to ensure that the on-chip digital logic and state machines initialize to the proper conditions at power-up and after brownout events. This POR senses the supply voltage and holds the logic in the initialization state until the supply voltage reaches the required operating level. The MAX1452/MAX1455 operate from two supply inputs: (1) VDD
, which powers the internal logic and the analog circuits, and (2) VDDF
, which powers the on-chip EEPROM memory circuits. At the system level, VDD
are tied together either directly or through a resistor (as described below).
In a typical application circuit, there is an RC circuit on the VDDF
pin (R between VDD
, and C between VDDF
and GND). The RC filter is required because, due to cost and space constraints, the chosen VDD
supply normally has limited driving capability and the VDD
level cannot be maintained during EEPROM operations. As a result of this limited drive capability, potential issues can arise during manufacturing and/or operation. One of these issues is starting up in the wrong mode—if a problem occurs, the output will start in digital mode instead of starting in analog mode. This generally happens because VDDF
will grossly lag VDD
and causes unreliable reading of the Control Location in the flash memory. A second issue is the output noise caused by ripples on VDD
that can couple through to the output. Finally, EEPROM cell charging can be compromised after a WRITE operation. In applications where a VDD
supply with adequate current capability is selected, none of these issues will be present.
The MAX1452/MAX1455 contain an integrated EEPROM to store calibration coefficients and device configuration information. Depending on the EEPROM operation performed, the current drawn from the VDDF
supply is 7mA to 25mA. When active, the EEPROM has three operational modes: Read, Write, and Erase. Both Write and Erase operations are used during module manufacturing for calibration and testing (in digital mode). After manufacturing, the device is locked (switched to analog mode) and only the Read operation is performed. It is important to note that the high current levels for Write and Erase operations occur only during manufacturing, and there is no requirement to account for them in the application circuit design.
In manufacturing, the EEPROM operations can draw about 25mA from VDDF
during calibration and testing. The Erase operation draws 25mA for 1µs, followed by a 16mA current draw for 5ms. The Write operation draws 25mA for 1µs, followed by a 16mA current draw for 80µs.
During normal operation, there are 10 EEPROM Read operations every 1ms to load or refresh the coefficient and configuration registers. Each Read operation draws a current of 7mA for 1µs and no current for 1µs. The result is a burst of 10 closely spaced Read operations that occurs every 1ms, resulting in a low effective average current draw on VDDF
In MAX1452/MAX1455 applications, the VDD
supply must be properly sized to supply the currents required for EEPROM operations (especially in the case of a 4-20mA application). Without sufficient current sourcing, the VDDF
voltages may drop below the minimum guaranteed operating voltage of 4.5V.
When the internal EEPROM performs a Read operation during the MAX1452/MAX1455’s normal operating mode, voltage ripples on VDDF
may occur. In the case of a weak VDD
supply, these voltage ripples could couple onto VDD
, creating undesired output noise. The chip’s separate VDD
supply pins allow user applications to incorporate external RC filtering on the VDDF
supply pin to reduce unwanted noise coupling. However, there are many considerations to be made when choosing the RC filter values. The value of R must be large enough to prevent current spikes on VDD
during EEPROM operations. R must also be small enough to allow VDDF
to closely track the VDD
voltage during initial startup to prevent any startup problems. Of course, the selection of C is also of great importance, and there is an optimal mix of R and C values. However, the optimal values in this case may not address all concerns.
Add a Diode to Address Issues Caused by a Weak VDD Supply
To utilize an RC filter on VDDF
for output noise improvement without being subjected to undesirable consequences, one can add a Schottky diode between the VDD
in parallel with R of the RC filter (Figure 1
). The forward voltage of this Schottky diode must be smaller than the forward voltage of the parasitic diode between VDD
and GND, and also large enough such that it does not conduct at the maximum operating temperature of the product. A BAT54
Schottky diode, with a forward voltage of 300mV at +25°C, has been tested and proved suitable for this application. Such a diode between the VDD
results in the following improvements:
Figure 1. This typical MAX1452 application circuit also includes a Schottky diode to address VDD supply drive limitations.
- Resolution of the startup problem. This diode allows VDDF to track the VDD voltage very closely—only one diode drop (< 300mV) apart. Consequently, when the POR signal is released, the VDDF voltage is at the proper level to correctly read the Control Location in the EEPROM, thereby starting in correct operating mode.
- Decreased output noise. Adding the diode, it is possible to use much larger values of C (a minimum of 0.47µF is required to maintain the VDDF level during high current draw in Read operation) and R (typically 1kΩ). Larger RC values may be used without causing a concern at startup. Regardless of the RC-filter time constant, VDD and VDDF are always only one diode drop (< 300mV) apart. Without the diode, during the Read operation, too large a C value causes a large delay in VDDF ramp and could result in a startup problem. Also, too small a C value causes larger VDD spikes that propagate through the output, causing unwanted output noise.
- Improved EEPROM cell charging when writing to the EEPROM. This improvement occurs because the VDDF level remains above the minimum required 4.5V (VDD = 5V) at all times.