In the TD-SCDMA system specification, a subframe consists of seven regular slots and one special slot. The first regular slot (TS0) is always assigned to downlink, while the second regular slot (TS1) is for uplink. The special slot is allocated between TS0 and TS1 for downlink and uplink frequency synchronization and for providing a guard gap from downlink to uplink. After TS1, the system may go back to downlink again later at some slots depending on the data length being transmitted. Occasionally, a handset needs to switch back to downlink immediately after uplink slot(s), as seen in Figure 1
. This requires a very fast switching speed for the handset, as the guard period is only 12.5µs between the uplink and downlink. The challenges in meeting this switching requirement are as follows:
- If the receiver turns on after the Tx slot ends, the DC offset of the zero-IF receiver cannot be removed within the guard period.
- If the receiver turns on within the Tx slot, the Tx signal will saturate it due to limited Tx/Rx switch isolation.
Figure 1. The T3R4 scenario in a TD-SCDMA system.
The MAX2392 Solution
is a zero-IF receiver that adequately meets the T3R4 system requirements with carefully devised control timing.
The DC-cancellation architecture in the MAX2392 is equivalent to two stages of high-pass filtering (diagram shown in Figure 2). The filter following the mixer is intended to remove DC artifacts of the mixer. The post-VGA filter cancels DC offsets generated in the VGA. The high-pass corner of these filters is 8.6kHz during normal operation, but can be set to 1MHz for fast settling.
If the high-pass filters are set to 1MHz and the LNA is disabled, saturation of the receiver can be avoided during the Tx slot. However, this is dependant on the Tx/Rx switch isolation. If the isolation of the Tx/Rx switch is not sufficiently high, a switch may be needed before the LNA to avoid Rx saturation by the Tx signal.
Figure 2. Diagram of the MAX2392 high-pass filtering stages.
When the Tx slot finishes, the LNA switches to ON in high-gain mode; the high-pass corner then reverts to 8.6kHz (nom) after the DC offsets are settled.
A control timing diagram for the T3R4 scenario using the MAX2392 is depicted in Figure 3.
Figure 3. A diagram of the T3R4 scenario's control timing using the MAX2392.
Experiments have demonstrated that the MAX2392 successfully meets TD-SCDMA T3R4 system requirements using the aforementioned control sequence.