APPLICATION NOTE 358

DS3134 Application Note: PCI Bus Utilization


Abstract: This application note shows how the bus utilization, the available bandwidth and the bus cycles per packet that are required by the DS3134 can be calculated.


Overview
The DS3134 accesses the PCI bus to obtain and store HDLC packets as they are sent and received. This application note details how to calculate how much of the available bus bandwidth will be required by the DS3134 to operate properly. Hopefully, with the information provided in the application note, the user can modify the numbers to fit their particular application. Refer to Table 1 to reference the variables used in this article.

Table 1. Definition Of Variables

Variable Definition Valid Range
B Average number of packets processed before the host updates the receive-free queue and transmit
pending queue or reads the receive-done queue and transmit-done queue.
1, 2, 3, ....
C Average number of bus cycles required per packet. 1, 2, 3, ....
D Number of bus cycles needed for data to be transferred. 1, 2, 3, ....
P Size of the Packet in bytes (always 64 in this application note). 64
R Average number of bus cycles added due to latency in RAM access. 0, 1, 2, ....
X Average number of bus accesses required to send/obtain packet data to/from the data buffers. 1, 2, 3, ....


Types Of Bus Accesses
There are four types of bus accesses that are performed either by the DS3134 or by the host to support the DMA in the DS3134. In the following descriptions, the variable D is defined as the number of data cycles and the variable R is defined as the number of bus cycles needed due to RAM access latency.

Type 1: Burst Read by the DMA from the Host RAM
The total number of bus cycles required when the DMA burst reads from the host RAM is [3+R+D]. This equation was derived from Figure 9.1B of the DS3134 data sheet and as shown below.

Cycle No. Cycles
Required
Address Cycle 1
Turn Around Cycle 1
RAM Access Latency Cycles R
Data Cycles D
Turn Around Cycles 1

Type 2: Burst Write by the DMA to the Host RAM
The total number of bus cycles required when the DMA burst writes to the Host RAM is [2+R+D]. This equation was derived from Figure 9.1C of the DS3134 data sheet and as shown below.

Cycle No. Cycles
Required
Address Cycle 1
RAM Access Latency Cycles R
Data Cycles D
Turn Around Cycles 1

Type 3: Write by the Host to the DS3134
The total number of bus cycles required when the host writes to the DS3134 is 7.

Type 4: Read by the Host to the DS3134
The total number of bus cycles required when the Host reads from the DS3134 is 7. Note: For Type 3 and 4, the 7-cycle is inherent to Chateau and cannot be changed.

Number Of Bus Cycles Needed Per Packet
In order to calculate bus utilization, the number of bus cycles required must be known. To obtain this number, several assumptions have been made and are listed below. Figure 1 shows the standard sequence that the Host and DMA will follow for each packet received or transmitted. From Figure 1 we can create a formula to calculate the average number of bus cycles required per packet, which is the variable C.

Receive Side
Cr = [(3 + R + 24) / 12] + [(P / 4) + (2 + R)X] + [2 + R + 3] + [(2 + R + 6) / 6] + [4(7 / B)]

Transmit Side
Ct = [(3 + R + 12) / 12] + [2 + R + 1] + [3 + R + 4] + [(P / 4) + (3 + R)X] + [(2 + R + 6) / 6] + [4(7 / B)]

Total Formula
C = 21.16 + 3.5R + 0.5P + 56 / B + (5 + 2R)X

Assumptions Made to Calculate the Number of Bus Cycles Required Per Packet

  • All packets are 64 bytes (seen as worse case).
  • The FCS of the HDLC packet is not transferred to or from the PCI bus.
  • On the receive side, only large buffers are used (small buffers are disabled).
  • The receive DMA will burst read the free queue and burst write to the done queue.
  • The transmit DMA will burst read the pending queue and burst write the done queue.
  • All packets fit within a single buffer (i.e., only one descriptor); reasonable since packets are 64 bytes.
  • All physical layer links are filled with packets, no idle codes sent or received.
  • Interrupt routines and overhead (like accesses to the local bus) are not considered.

Figure 1. Per Packet Bus Cycle Flowchart

Notes:

  1. 12 descriptors x 2 dwords= 24
  2. Packet in bytes, 4 bytes/data cycle
  3. 6 descriptors x 1 dword = 6


Figure 1 continued

Notes:

  1. 12 descriptors x 1 dword = 12.

Bus Utilization
With the known number of bus cycles required per packet, the bus utilization can be calculated. Bus utilization is defined as the number of bus cycles required by the DS3134 in a one second period divided by the total number of bus cycles available in one second which for the purposes of this Application Note will be 33,000,000 since the PCI clock rate is assumed to be 33MHz. The following two formulas can be used to calculate bus utilization.

Following are examples of three cases of bus utilization. In each case, it was assumed that all the incoming and outgoing packets were 64 bytes long (P = 64) and that the host would update and read the queues used by the DMA on the DS3134 on average, every eight packets (B = 8). In each case there are two scenarios. In scenario A, the host RAM is tightly coupled and on average only adds one bus cycle for each access. In scenario B, the host RAM is not tightly coupled and on average adds seven bus cycles for each access. These three examples can be modified to fit the exact application.

Table 2. Description of Examples

Case Description No. of Packets Per Second
Per HDLC Channel
Case 1 256 channels at 64kbps 125
Case 2 64 clear-channel T1 3000
Case 3 2 clear-channel T3 84000

Table 3. Examples of Bus Utilization
Case R P B X No. of Bus Cycles
Required Per Packet [C]
Bus Utilization (%)
1A 1 64 8 3 84.7 8.2
1B 4 4 8 3 113.2 11.0
2A 1 64 8 1 70.7 41.1
2B 4 64 8 1 87.2 50.7
3A 1 64 8 1 70.7 36.0
3B 4 64 8 1 87.2 44.4

Assumption: B = 8; Cases A, R = 1; and Cases B, R = 4.

NOTES:
Packets per second: (speed of HDLC channel) x (1 byte/8 bits) / (bytes per packet)
Example, Case 1: 64000bps x (1/8) / 64 bytes = 125

Case 1

  1. There are 1024 blocks in the Chateau internal FIFO, each block is 4 dwords (16 bytes). With 256 channels loaded, each channel can only be assigned to 1024 / 256 = four blocks (4 x 16 = 64 bytes / channel).
  2. Since each FIFO block is 64 bytes, a 64-byte packet in the FIFO can fill or empty in two bus accesses. For worst-case assumptions, we use three in this example.
Case 2
  1. There are 64 channels in Case 2, and, therefore, the block size in the FIFO can be 1024 / 64 = 16 blocks (16 x 16 = 256 bytes/channel).
  2. Each FIFO block size is 256 bytes; therefore, a 64-byte packet in the FIFO can fill or empty in one bus access.
Case 3
  1. There are two channels in Case 3, and, therefore, the block size in the FIFO can be 1024 / 2 = 512 blocks (512 x 16 = 8192 bytes/channel).
  2. Each FIFO block size is 8192 bytes; therefore, a 64-byte packet in the FIFO can be fill or empty in one bus access.

Revision History
Version Date Changes
1 02/24/98 Original Release
2 12/2/98
  1. Corrected the formulas on page 2 from 4(B/7) to 4(7/B) and from 1.143B to 56/B.
  2. Changed R & X values in Table 4 to reflect more realistic values.
  3. Corrected minor grammatical errors.
3 03/02/99
Modified by Ming
  1. Added borders to tables.
  2. Added a few notes to clarify some assumptions and constants.
  3. Change the symbol X on page 4 equation to 8.
4  
  1. Correct typo on page 2 by removing the extra term ?+ [2 + R + 3]? from equation Ct.
5 2/20/01
  1. Corrected table on page 2 by removing "Turn Around Cycle" from table.
  2. Corrected grammatical errors, added notes on page 3.


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APP 358:
APPLICATION NOTE 358,AN358, AN 358, APP358, Appnote358, Appnote 358