Keywords: T1, E1, T1/E1, single chip transceivers, SCTs
Table 1. Dallas Semiconductor 100-Pin LQFP Single Chip Transceivers
|Interleaved PCM Bus||X||X||X||X|
JTAG, IEEE 1149.1 Boundary Scan Architecture
The new DS21352/354/552/554 SCTs will incorporate JTAG's Boundary Scan Architecture (IEEE 1149.1). The Framer ModeSelect (FMS) pin has an internal 10k pull up resistor which places the new SCTs in the DS2152/54 legacy mode. All JTAG pins can be left unconnected in the legacy mode. To use the JTAG features, a hardware change will be required to incorporate the 5 JTAG pins and the FMS pin will need to be tied LOW. The FMS and JTRST pins will affect the TESTZ pin (all four DS21x5y) and the TEST1 and TEST0 bits in the TCR2 register (both DS21x52). See Table 2 for JTRST and FMS conditions. Table 3 lists the new pin descriptions for the 3.3V I/O on the DS215y and the new pin descriptions for the new features on the DS21352/354/552/554 SCTs. Table 1 summarizes all of the SCTs in the 100 pin LQFP packages.
Table 2. JTRST and FMS Conditions
|X||1||TESTZ pin, TEST1 bit and TEST0 bits in TCR2 of DS21x52 enabled.|
|0||0||TEST1 bit and TEST0 bits in TCR2 of DS21x52 enabled.|
|1||0||0 TESTZ disabled, TEST1 and TEST0 bits in TCR2 of DS21x52 disabled.|
|76||NC||FMS||I||Framer Mode Select [FMS]. Selects the DS2152/54 mode when HIGH or the DS21x52/x54 mode when LOW. If High, the JTRST is internally pulled LOW. If LOW, JTRST has normal JTAG functionality. This pin has a 10k pull up resistor.|
|5||NC||JTRST||I||IEEE 1149.1 Test Reset [JTRST]. This signal is used to asynchronously reset the test access port controller. At power up, JTRST must be toggled from LOW to HIGH. This action will set the device into the DEVICE ID mode allowing normal device operation. This pin has a 10k pull up resistor. When FMS=1, this pin is tied LOW internally. Tie JTRST LOW if JTAG is not used and the framer is in DS21x5y mode (FMS LOW).|
|2||NC||JTMS||I||IEEE 1149.1 Test Mode Select [JTMS]. This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1 states. This pin has a 10k pull up resistor.|
|4||NC||JTCLK||I||IEEE 1149.1 Test Clock Signal [JTCLK]. This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.|
|7||NC||JTDI||I||IEEE 1149.1 [JTDO]. Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pull up resistor.|
|10||NC||JTDO||O||IEEE 1149.1 [JTDO]. Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected.|
|36||NC||CI||I||Carry In [CI]. Input. A rising edge on this pin causes RSER and RSIG to come out of HIGH Z state and TSER and TSIG to start sampling on the next rising edge of RSYSCLK/TSYSCLK beginning an I/O sequence of 8 or 256 bits of data.|
|54||NC||CO||O||Carry Out [CO]. An output which is set HIGH when the last bit of the 8 or 256 IBO output sequence has occurred on RSER and RSIG.|
Interleaved PCM Bus Operation (IBO)
The new DS21352/354/552/554 SCTs have a feature which will allow multiple SCTs to share a PCM bus for data or signaling. This is possible by internally gating the RSYSCLK and TSYSCLK inputs on the SCTs. When this feature is enabled 2 or 4 SCTs can share a 4.096 MHz or 8.192 MHz bus respectively. There are 4 register bits and two hardware pins which control the Interleaved Bus Operation (IBO). Using the IBO, the user must first set the IBOEN bit to a logic 1. Then select the byte or frame interleave mode via the INTSEL bit. MSEL1 and MSEL2 together determine both the slave or master mode for that specific SCT and how many SCTs are being multiplexed together. Two devices will require a 4.096 MHz clock to be applied to RSYSCLKs and TSYSCLKs while four devices will require an 8.192 MHz clock. The elastic stores need to be enabled and set in the 2.048 MHz mode. Figure 1 shows the appropriate hardware connections.
Figure 1. Hardware connections for IBO.
The master SCT will not use the CI pin but will use the RSYNC/TSSYNC pins instead. The CI pin for the master SCT should be tied LOW. Each frame or multiframe SYNC/TSSYNC input signal will reset the IBO counters for each SCT and will enable the I/O of the master SCT to move 8 or 256 bits depending on byte or frame interleaving. On the 8th or 256th bit, the master CO pin will go HIGH. This signal can be used for the next SCT's CI pin. If at any time there is a new frame or multiframe RSYNC/TSSYNC input signal asynchronous to the existing frame or multiframe boundary, the IBO counters will be reset on the master SCT and each of the slaves. When an SCT is not actively outputting data, the RSER and RSIG pins will be in HIGH Z state. See Figure 2 for timing constraints and Table 6 for setup and delay times for CI and CO.
Figure 2. IBO timing.
|Register Bit||Description||Logic '0'||Logic '1'|
|IBOEN||Interleaved Bus Operation Enable||IBO disabled||IBO disabled IBO enabled. In this mode,
TSYSCLK and RSYSCLK must
be connected together and elastic stores must be enabled in the 2.048 MHz mode.
|INTEL||Interleave Select||Byte interleave||Frame interleave.|
|MSEL1||Master Select bit 1||See Table 5||See Table 5|
|MSEL2||Master Select bit 2||See Table 5||See Table 5|
|1||0||Master Device With 1 Slave Device (4.096 MHz Clock)|
|0||1||Master Device With 3 Slave Device (8.192 MHz Clock)|
|Setup time for CI||t1||20||ns|
|Delay time after a rising edge on SYSCLK/TSYSCLK.
CO will stay HIGH for a full RSYSCLK/TSYSCLK period.
Transmit Clock Mux Control
The DS2152 and DS2154 have a Loss of Transmit Clock Mux Control (LOTCMC) bit in the TCR1 and CCR2 control registers respectively. Enabling these bits allows TCLK to be connected to RCLKO internally if no transition occurs at TCLK. The new TCMC bit enables TCLK to be connected to RCLKO internally regardless of the condition on the TCLK pin.